利用WAT資料建構晶圓良率預測模型之研究

Modeling of Wafer Die Yield by WAT Parameters

張秉裕(Ping-Yu Chang)；陳琨太(Kuen-Tai Chen)；王振宇(Chen-Yu Wang)

晶圓良率 ； 晶圓允收測試 ； 類神經網路 ； yield model ； wafer acceptance test ； neural network

品質學報

18卷6期（2011 / 12 / 01）

519 - 538

繁體中文

隨著半導體生產技術的發展與進步，以及晶圓生產尺寸面積的增大，良率高低一直被半導體產業視為能否獲利的重要指標，因此良率預測模式已然成為半導體產業中相當重要的一個討論議題。早期的研究大多使用晶圓的缺陷數及晶圓面積等變數配合一固定的分配建構良率預測模式，但隨著製程的進步及晶圓面積的增加，晶圓缺陷的分佈有隨機及系統性因素所構成，因而加入了缺陷群聚指標來加以修正模型以提高預測準確度，不過此等固定分配之預測模式並不一定適合於每一種半導體製程，且有可能造成良率預測的不準確及不可靠。本研究利用晶圓允收測試（Wafer Acceptance Test, WAT）資料與晶圓針測良率（Circuit Probe Yield, CP）間之相關性，篩選WAT參數以減少輸入變數的數目，並藉由倒傳遞類神經網路（Backpropagation Neural Network, BPNN）、廣義迴歸類神經網路（General Regression Neural Network, GRNN）及集群資料處理技術（Group Method of Data Handling, GMDH）等分析方法，提出一簡便、有效率且準確度高的良率預測模式，以提供半導體業者於良率管理作業之參考。研究結果顯示使用倒傳遞類神經網路進行晶圓允收測試參數的選取，再配合集群資料處理技術建構良率模型，可達到有效縮減輸入變數、簡化預測模型的目標，且對良率的預測能夠有足夠的準確度及良好的預測效果。

Wafer die yield is a key index of business profit at the semiconductor industry as the development of the semiconductor production technology and wafer size increases. Thus, the wafer die yield prediction models become a very important issue to this industry. Early researches mostly use such parameters as defects on wafer and wafer size cooperate with a regular distribution, such as Poisson distribution or Negative Binomial distribution, to establish the wafer die yield prediction model. However, these prediction methods of yield models might not be suitable and accurate for all semiconductor manufacturers. In this study, we discover the connection between the wafer acceptance test (WAT) data and circuit probe yield. A simple, efficient and accurate wafer die yield prediction model with less WAT parameters is proposed. Various Neural Network analysis techniques such as Backpropagation Neural Network (BPNN), General Regression Neural Network (GRNN) and Group Method of Data Handling (GMDH) are analyzed and compared. Our Result shows Backpropagation Neural Network is valid and efficient in selecting WAT parameters. The GMDH is recommended for establishing the model because of its ability to catch data pattern with less variables and higher accuracy.

1. Collica, R. S.(1993).A logistic regression yield model for sram bit fail patterns.Proceedings of IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
2. El-Kareh, B.,Ghatalia, A.,Satya, A.V. S.(1995).Yield management in microelectronic manufacturing.Proceedings of Electronic Components and Technology Conference
3. Hsu, S. C.,Chien, C. F.(2007).Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing.International Journal of Production Economics,107(1),88-103.
4. Jun, C. H.,Hong, Y.,Kim, S. Y.,Park, K. S.,Park, H.(1999).A simulation-based semiconductor chip yield model incorporating a new defect cluster index.Microelectronics Reliability,39(4),451-456.
5. Kondo, T.,Pandya, A. S.,Nagashino, H.(2007).GMDH-type neural network algorithm with a feedback loop for structural identification of RBF neural network.International Journal of Knowledge-Based and Intelligent Engineering Systems,11(3),157-168.
6. Murphy, B. T.(1964).Cost-size optima of monolithic integrated circuits.Proceedings of the IEEE,52(12),1537-1545.
7. Okabe, T.,Nagata, M.,Shimada S.(1972).Analysis on yield of integrated circuits and a new expression for the yield.Electrical Engineering in Japan,92(6),135-141.
8. Raghavachari, M.,Srinivasan, A.,Sullo, P.(1997).Poisson mixture yield models for integrated circuits: a critical review.Microelectronics Reliability,37(4),565-580.
9. Seeds, R. B.(1967).Yield and cost analysis of bipolar LSI.Proceedings of the IEEE International Electron Devices Meeting,Piscataway, NJ:
10. Specht, D. F.(1991).A general regression neural network.IEEE Transactions on Neural Networks,2(6),568-576.
11. Stapper, C. H.(1989).Large-area fault clusters and fault tolerance in VLSI circuits: a review.IBM Journal of Research and Development,33(2),162-173.
12. Stapper, C. H.(1989).Small-area fault clusters and fault tolerance in VLSI circuits.IBM Journal of Research and Development,33(2),174-177.
13. Stapper, C. H.(1973).Defect density distribution for LSI yield calculations.Proceedings of IEEE Transactions on Electron Devices,20(7),655-657.
14. Stapper, C. H.(1991).On murphy's yield integral.IEEE Transactions on Semiconductor Manufacturing,4(4),294-297.
15. Tong, L. I.,Lee, W. I.,Su, C. T.(1997).Using a neural network-based approach to predict the wafer yield in integrated circuit manufacturing.Proceedings of IEEE Transactions on Components, Packaging, and Manufacturing Technology,20(4),288-294.
16. Wong, A. Y.(1996).A statistical parametric and probe yield analysis methodology.Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
17. 李靜宜(2003)。碩士論文(碩士論文)。國立交通大學工業工程與管理研究所。
18. 林瑞山(2004)。碩士論文(碩士論文)。國立成功大學工程管理研究所。
19. 許文輝(1999)。碩士論文(碩士論文)。元智大學工業工程研究所。
20. 許志瑋(2003)。碩士論文(碩士論文)。國立交通大學工業工程與管理研究所。
21. 傅旭正(1999)。碩士論文(碩士論文)。國立交通大學工業工程與管理研究所。
22. 楊博欽(2004)。碩士論文(碩士論文)。國立交通大學工業工程與管理研究所。
23. 劉亭宜(1999)。碩士論文(碩士論文)。元智大學工業工程研究所。
24. 蔡文傑(2004)。碩士論文(碩士論文)。國立交通大學工業工程與管理研究所。