具有不同界面層材料之奈米級高介電絕緣層互補金氧半場效應電晶體研究

Analysis on Characteristics of Nanometer-Scale CMOSFETs with Different Interfacial Layer Using High-K Dielectric Multilayer

10.29688/MHJ.201102.0007

陳啓文(Chii-Wen Chen)；許志謙(Chih-Chien Hsu)；賴信誠(Hsin-Cheng Lai)；葉文冠(Wen-Kuan Yeh)；陳育廷(Yu-Ting Chen)

高介電係數 ； 閘極漏電流 ； 界面層 ； 電荷汲引技術 ； high dielectric constant ； gate leakage current ； interface layer ； Charge Pumping technology

明新學報

37卷1期（2011 / 02 / 01）

77 - 83

繁體中文

本文研究高介電係數閘極電晶體，在不同界面層製程方式與不同界面層材料條件下，比較元件的基本電性，以及透過電荷汲引技術研究電荷捕捉／散逸效應，對界面陷阱密度大小及分佈，進而瞭解到閘極氧化層之元件電荷特性與界面品質。實驗發現界面層製造材料選用二氧化矽（RT○ plasma製程）比氮氧化矽（RTN○ plasma製程）有較低的界面缺陷，具有較小的閘極漏電流與較佳的電性。透過元件劣化實驗後，界面層材料為二氧化矽之元件，有較佳的可靠度，也觀察到元件經過劣化後，會使得界面缺陷數量增加。

In this paper, components of basic electrical high-k gate transistors High dielectric constant in different interface layer manufacturing methods are compared with different interfacial layer materials. In order to figure out the gate oxide charge device and interface characteristics of quality, the conditions were manipulated, such as Charge Pumping Technique charge trapping/dissipation effect, interface trap density, size and distribution. It was found that the effects of using the silicon dioxide interface layer material of choice (RTO plasma process) are more effective than those of using the nitrogen oxide (RTNO plasma process). The products of the RTO process have a lower interface defect, with a smaller gate leakage current and better electrical properties than those of RTNO processing. Although the interfacial defects increased after stress, we concluded that the interface layer with silicon dioxide has better reliability.

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