SIMULTANEOUS TEST SCHEDULING AND TAM BUS WIRE ASSIGNMENT FOR TEMPERATURE-DEPENDENT CORE-BASED SOC TESTING

10.6329/CIEE.2016.2.03

Shih-Hsu Huang；Ching-Chun Chiu；Chun-Hua Cheng；Te-Jui Wang

Reliability ； System-on-Chip ； Temperature ； Test Access Mechanism ； Test Scheduling

電機工程學刊

23卷2期（2016 / 04 / 01）

53 - 62

英文

Recent researches have shown that temperature-dependent testing, which applies different tests at different temperature ranges, is necessary for core-based system-on-chip SoC designs. However, previous temperature-dependent test scheduling approaches assume that two tests cannot utilize the test-access mechanism (TAM) at the same time. In fact, if the tests of different cores do not use the same TAM bus wire, they can be executed concurrently for reducing the test application time. Based on this observation, in this paper, we propose a two-phase algorithm to perform the simultaneous application of test scheduling and TAM bus wire assignment for temperature-dependent core-based SoC testing. Compared with previous approaches, benchmark data consistently show that the proposed approach can greatly reduce the total test application time.

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