Parallel Hardware Architectures for the Cryptographic Tate Pairing

10.6633/IJNS.200807.7(1).04

Guido M. Bertoni；Luca Breveglieri；Pasqualina Fragneto；Gerardo Pelosi

Area-time tradeoff ； parallelism ； scheduling ； Tate pairing

International Journal of Network Security

7卷1期（2008 / 07 / 01）

31 - 37

英文

Identity-based cryptography uses pairing functions, which are sophisticated bilinear maps defined on elliptic curves. Computing pairings efficiently in software is presently a relevant research topic. Since such functions are very complex and slow in software, dedicated hard ware (HW) implementations are worthy of being studied, but presently only very preliminary research is available. This work affords the problem of designing parallel dedicated HW architectures, i.e.,co-processors, for the Tate pairing, in the case of the Duursma-Lee algorithm in characteristic 3. Formal scheduling methodologies are applied to carry out an extensive exploration of the architectural solution space, evaluating the obtained structures by means of different figures of merit such as computation time, circuit area and combinations thereof. Comparisons with the (few) existing proposals are carried out, showing that a large space exists for the efficient parallel HW computation of pairings.