應用於有線及無線系統以數位時間轉換器實現之鎖相迴路及除頻器設計

Digital-to-Time Converter Based Phase-Locked Loop and Frequency Divider Design for Wireline and Wireless Applications

10.6342/NTU201800326

王敦儒

相位選擇器 ； 鎖相迴路 ； 展頻 ； 取樣鎖定 ； 除頻器 ； Phase Selector ； Spread-Spectrum ； Phase-Locked Loop ； Sub-Sampling ； Frequency Divider

臺灣大學電子工程學研究所學位論文

2018年

碩士

林宗賢

英文

數位時間轉換器 (DTC) 被廣泛運用於各種時脈相關的應用，例如小數型鎖相迴路電路. 一個數位時間轉換器的延遲是由一個數位的控制碼來決定，延遲長度通常是從一組離散的元件中開啟特定的數量來控制，例如選取特定數量的延遲單位或是特定數量的充電電容。本論文將討論數位時間轉換器的應用。 本論文包含兩個作品，第一個作品為十五億赫茲以取樣鎖定鎖相迴路實現應用於展頻之時脈產生器，使用取樣鎖定(sub-sampling)之架構實現，並支援展頻調變。此作品的應用為有線系統中的時脈產生器，目標為降低對鄰近設備的電磁干擾量。本展頻時脈產生器實現於TSMC 180奈米製程。量測結果顯示本展頻時脈產生器在展頻調變開啟時，有18.98 dB之電磁干擾抑制。此外，輸出訊號量測得到之方均根時基誤差(RMS Jitter)為0.88 ps。此作品在1.8伏特下功率消耗為11.1毫瓦。 第二個作品為以相位切換實現之多輸出小數除頻器，使用相位切換之架構，支援多個不同頻率輸出，輸出頻率範圍為0.635-162.5 MHz。此作品的應用為供給單一系統晶片內，操作於不同頻率的各個子電路。以單一時脈產生器搭配數個本作品之除頻器，可節省多個不同頻率時脈產生器的面積以及功率消耗。本除頻器以TSMC 90奈米製程實現。量測結果顯示在不同的除數底下，本除頻器都能正確的運作。此作品並且可以同時支援不同除數，達到單一時脈輸入，雙時脈輸出的功能。

Digital-to-Time converters (DTC) have been widely used and it serves as one of the building blocks in many timing applications, such as the fractional-N PLL. The delay is of a DTC is controlled by a digital code, and the amount of delay is usually varied by switching on/off of a set of discrete elements, such as unit delay cells or charging capacitors. This thesis focuses on the applications of DTC. This thesis includes two works. The first work is “A 1.5-GHz Sub-Sampling Fractional-N PLL for Spread-Spectrum Clock Generator”. This work employs a fractional-N sub-sampling PLL, and supports spread-spectrum clocking. This work aims to reduce the electromagnetic interference (EMI) of a clock generator with its neighboring devices. It is fabricated in TSMC 180-nm CMOS process. Measurement results have shown that the EMI reduction with spread-spectrum clocking enabled is 18.98 dB. Measured RMS jitter of the output signal is 0.88 ps. With a 1.8-V supply voltage, the power consumption is measured to be 11.1 mW. The second work is “A 0.635~162.5 MHz Multiple Output Fractional Divider Using Phase Rotating Technique”. This work is realized by phase rotating technique, supporting multiple frequency outputs, with output frequency range of 0.635-162.5 MHz. This work aims to reduce the number of clock generators in a single SoC. It is fabricated in TSMC 90-nm CMOS process. Measurement results show that the proposed fractional divider functions properly under both integer and fractional division. Furthermore, this work supports dual outputs with two different division ratios, realizing a single input, multiple outputs frequency divider.

1. [1] R. Monteiro, B. Borges and V. Anunciada, “EMI Reduction by Optimizing the Output Voltage Rise Time and Fail Time in High-Frequency Soft-Switching Converters,” in IEEE 35th Annual Power Electronics Specialists Conference, vol.2, pp. 1127-1132, 2004.
   連結：
2. [2] K. Hardin, R. A. Oglesbee and F. Fisher, “Investigation into the Interference Potential of Spread-Spectrum Clock Generation to Broadband Digital Communications,” in IEEE Transactions on Electromagnetic Compatibility, vol. 45, no. 1, pp. 10-21, Feb. 2003.
   連結：
3. [3] H. R. Lee, O. Kim, G. Ahn and D. K. Jeong, “A Low-Jitter 5000ppm Spread Spectrum Clock Generator for Multi-Channel SATA Transceiver in 0.18μm CMOS,” in IEEE International Solid-State Circuits Conference, vol. 1, pp. 162-163, 2005.
   連結：
4. [4] Y. H. Kao and Y. B. Hsieh, “A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial Advanced Technology Attachment Applications Using Two-Point Modulation,” in IEEE Transactions on Electromagnetic Compatibility, vol. 51, no. 2, pp. 245-254, May 2009.
   連結：
5. [5] S. Jang, S. Kim, S. H. Chu, G. S. Jeong, Y. Kim and D. K. Jeong, “An All-Digital Bang-Bang PLL Using Two-Point Modulation and Background Gain Calibration for Spread Spectrum Clock Generation,” in Symposium on VLSI Circuits, pp. C136-C137, 2015.
   連結：
6. [6] H. H. Chang, I. H. Hua and S. I. Liu, “A Spread-Spectrum Clock Generator with Triangular Modulation,” in IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 673-676, Apr. 2003.
   連結：
7. [7] C. Y. Yang, C. H. Chang and W. G. Wong, “A ∆∑ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 1, pp. 51-59, Jan. 2009.
   連結：
8. [8] Y. B. Hsieh and Y. H. Kao, “A Fully Integrated Spread-Spectrum Clock Generator by Using Direct VCO Modulation,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 7, pp. 1845-1853, Aug. 2008.
   連結：
9. [9] D. De Caro, C. A. Romani, N. Petra, A. G. M. Strollo and C. Parrella, “A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1048-1060, May 2010.
   連結：
10. [10] K. H. Cheng, C. L. Hung and C. H. Chang, “A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique,” in IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1198-1213, May 2011.
    連結：
11. [11] X. Gao, E. A. M. Klumperink, M. Bohsali and B. Nauta, “A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2,” in IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, Dec. 2009.
    連結：
12. [12] W. S. Chang, P. C. Huang and T. C. Lee, “A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector,” in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2964-2975, Dec. 2014.
    連結：
13. [13] C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli and Z. Wang, “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology,” in IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 1039-1045, July 2000.
    連結：
14. [14] A. Elkholy, A. Elshazly, S. Saxena, G. Shu and P. K. Hanumolu, “ A 20-to-1000MHz ±14ps Peak-to-Peak Jitter Reconfigurable Multi-Output All-Digital Clock Generator Using Open-Loop Fractional Dividers in 65nm CMOS,” in IEEE International Solid-State Circuits Conference, pp. 272-273, 2014.
    連結：
15. [15] A. A. Abidi, “Phase Noise and Jitter in CMOS Ring Oscillators,” in IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1803-1816, Aug. 2006.
    連結：
16. [16] A. Tharayil Narayanan et al., “A Fractional-N Sub-Sampling PLL Using a Pipelined Phase-Interpolator With an FoM of -250 dB,” in IEEE Journal of Solid-State Circuits, vol. 51, no. 7, pp. 1630-1640, July 2016.
    連結：
17. [17] B. Razavi, “Challenges in the Design of Frequency Synthesizers for Wireless Applications,” in Proceedings of Custom Integrated Circuits Conference, pp. 395-402, 1997.
    連結：
18. [18] S. G. Bae, G. Kim and C. Kim, “A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 10, pp. 1132-1136, Oct. 2017.
    連結：
19. [19] Y. W. Li, C. Ornelas, H. S. Kim, H. Lakdawala, A. Ravi and K. Soumyanath, “A Reconfigurable Distributed All-Digital Clock Generator Core with SSC and Skew Correction in 22nm High-k Tri-gate LP CMOS,” in IEEE International Solid-State Circuits Conference, pp. 70-72, 2012.
    連結：
20. [20] W. Grollitsch, R. Nonis and N. Da Dalt, “A 1.4ps RMS-Period-Jitter TDC-Less Fractional-N Digital PLL with Digitally Controlled Ring Oscillator in 65nm CMOS,” in IEEE International Solid-State Circuits Conference, pp. 478-479, 2010.
    連結：
21. [1] R. Monteiro, B. Borges and V. Anunciada, “EMI Reduction by Optimizing the Output Voltage Rise Time and Fail Time in High-Frequency Soft-Switching Converters,” in IEEE 35th Annual Power Electronics Specialists Conference, vol.2, pp. 1127-1132, 2004.
    連結：
22. [2] K. Hardin, R. A. Oglesbee and F. Fisher, “Investigation into the Interference Potential of Spread-Spectrum Clock Generation to Broadband Digital Communications,” in IEEE Transactions on Electromagnetic Compatibility, vol. 45, no. 1, pp. 10-21, Feb. 2003.
    連結：
23. [3] H. R. Lee, O. Kim, G. Ahn and D. K. Jeong, “A Low-Jitter 5000ppm Spread Spectrum Clock Generator for Multi-Channel SATA Transceiver in 0.18μm CMOS,” in IEEE International Solid-State Circuits Conference, vol. 1, pp. 162-163, 2005.
    連結：
24. [4] Y. H. Kao and Y. B. Hsieh, “A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial Advanced Technology Attachment Applications Using Two-Point Modulation,” in IEEE Transactions on Electromagnetic Compatibility, vol. 51, no. 2, pp. 245-254, May 2009.
    連結：
25. [5] S. Jang, S. Kim, S. H. Chu, G. S. Jeong, Y. Kim and D. K. Jeong, “An All-Digital Bang-Bang PLL Using Two-Point Modulation and Background Gain Calibration for Spread Spectrum Clock Generation,” in Symposium on VLSI Circuits, pp. C136-C137, 2015.
    連結：
26. [6] H. H. Chang, I. H. Hua and S. I. Liu, “A Spread-Spectrum Clock Generator with Triangular Modulation,” in IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 673-676, Apr. 2003.
    連結：
27. [7] C. Y. Yang, C. H. Chang and W. G. Wong, “A ∆∑ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 1, pp. 51-59, Jan. 2009.
    連結：
28. [8] Y. B. Hsieh and Y. H. Kao, “A Fully Integrated Spread-Spectrum Clock Generator by Using Direct VCO Modulation,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 7, pp. 1845-1853, Aug. 2008.
    連結：
29. [9] D. De Caro, C. A. Romani, N. Petra, A. G. M. Strollo and C. Parrella, “A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1048-1060, May 2010.
    連結：
30. [10] K. H. Cheng, C. L. Hung and C. H. Chang, “A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique,” in IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1198-1213, May 2011.
    連結：
31. [11] X. Gao, E. A. M. Klumperink, M. Bohsali and B. Nauta, “A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2,” in IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, Dec. 2009.
    連結：
32. [12] W. S. Chang, P. C. Huang and T. C. Lee, “A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector,” in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2964-2975, Dec. 2014.
    連結：
33. [13] C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli and Z. Wang, “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology,” in IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 1039-1045, July 2000.
    連結：
34. [14] A. Elkholy, A. Elshazly, S. Saxena, G. Shu and P. K. Hanumolu, “ A 20-to-1000MHz ±14ps Peak-to-Peak Jitter Reconfigurable Multi-Output All-Digital Clock Generator Using Open-Loop Fractional Dividers in 65nm CMOS,” in IEEE International Solid-State Circuits Conference, pp. 272-273, 2014.
    連結：
35. [15] A. A. Abidi, “Phase Noise and Jitter in CMOS Ring Oscillators,” in IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1803-1816, Aug. 2006.
    連結：
36. [16] A. Tharayil Narayanan et al., “A Fractional-N Sub-Sampling PLL Using a Pipelined Phase-Interpolator With an FoM of -250 dB,” in IEEE Journal of Solid-State Circuits, vol. 51, no. 7, pp. 1630-1640, July 2016.
    連結：
37. [17] B. Razavi, “Challenges in the Design of Frequency Synthesizers for Wireless Applications,” in Proceedings of Custom Integrated Circuits Conference, pp. 395-402, 1997.
    連結：
38. [18] S. G. Bae, G. Kim and C. Kim, “A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 10, pp. 1132-1136, Oct. 2017.
    連結：
39. [19] Y. W. Li, C. Ornelas, H. S. Kim, H. Lakdawala, A. Ravi and K. Soumyanath, “A Reconfigurable Distributed All-Digital Clock Generator Core with SSC and Skew Correction in 22nm High-k Tri-gate LP CMOS,” in IEEE International Solid-State Circuits Conference, pp. 70-72, 2012.
    連結：
40. [20] W. Grollitsch, R. Nonis and N. Da Dalt, “A 1.4ps RMS-Period-Jitter TDC-Less Fractional-N Digital PLL with Digitally Controlled Ring Oscillator in 65nm CMOS,” in IEEE International Solid-State Circuits Conference, pp. 478-479, 2010.
    連結：