應用於生命訊號偵測雷達之2-30-GHz接收機與寬頻鎖相迴路前端電路之設計

Design of a Wideband PLL Front-End and a 2-to-30-GHz Receiver for Noncontact Vital Sign Detection

10.6342/NTU201700274

鄭人豪

互補金屬氧化物半導體 ； 壓控振盪器 ； 注入鎖定式除頻器 ； 生命訊號偵測雷達 ； 鎖相迴路 ； 接收機 ； CMOS ； voltage-controlled oscillator (VCO) ； injection-locked frequency divider (ILFD) ； vital sign detection radar (VSDR) ； phase-locked loops (PLL) ； receiver

臺灣大學電信工程學研究所學位論文

2017年

博士

黃天偉

英文

本論文呈現單晶微波積體電路(MMICs) 在互補金屬氧化物半導體 (CMOS) 的研究與實現以及應用於生命訊號偵測雷達之接收機整合。 本論文內容可分為三部分：分別為一寬頻可調之雙核壓控振盪器和一 寬頻鎖相迴路之前端電路、一鎖定頻寬為90.9％之注入鎖定除頻器和 一應用於生命訊號偵測雷達之2 至30 GHz 寬頻接收機。 首先是介紹利用切換電感和調整變容器之雙核壓控振盪器。利用90 奈米低功耗CMOS 技術，此雙核壓控振盪器已經完成設計與製造。 本文所提出之切換電感的方式，能不用直接在射頻訊號的路徑上，改 變LC 共振腔的電感值，對於諧振器的品質因數有最小的負載作用。此雙核壓控振盪器之可調頻率範圍為62.1% (從23.67 到45 GHz)。其平均輸出功率大約是−11 dBm，直流功率消耗則為16 至20 毫瓦。在操作頻率為23.67 GHz 的狀態下，所量測之相位雜訊於與1 MHz 的偏移頻率為−100.8 dBc / Hz。透過進一步整合此雙核壓控振盪器與一除4 之除頻器，我們利用相同製程實現了一寬頻鎖相迴路之前端電路。此除4 之頻率除頻器包括一基板偏壓之注入鎖定除頻器與源極注入電流模式除頻器(SICML)。該寬頻鎖相迴路前端電路之頻率操作範圍從23.6 到32 GHz（30.2 ％)。此電路之晶片面積為0.91 mm2，在1.2 V 與1.5 V 的供應電壓下，直流功耗為40.8 毫瓦。接著，第二個討論的電路是以90 奈米CMOS 技術實現一超寬鎖定頻寬之除2 注入鎖定除頻器。首先利用交叉耦合對與注入混頻之尺寸比進行最佳化以取得寬頻之鎖定頻寬。搭配峰化電感，正相基板偏壓，以及諧波抑制技術，所提出之除2 注入鎖定除頻器在注入功率為0 dBm 時，達到了90.9% 的鎖定頻寬(12 到32 GHz)。此電路之晶片面積為0.45 mm2。即使在注入功率為−10 dBm 時，此除2 之注入鎖定除頻器仍能維持32.9％的鎖定頻寬。在0.6 V 供應電壓下，其核心直流功耗只有2.4 毫瓦。最後，本論文亦提出一應用於寬頻生命訊號偵測雷達之2 到30GHz 寬頻接收機，使用0.18 微米的互補金屬氧化物半導體製程。寬頻生理訊號偵測雷達主要目的，是希望在不同的偵測環境，利用頻率多樣相來維持生理訊號偵測之準確度。此2 至30 GHz 接收機包含一高增益、低雜訊之分佈式放大器和一寬頻降頻混合器，其比例頻寬為175 %，可與雙頻帶發射機作進一步的整合在2 至30 GHz 之頻率範圍與本地訊號源功率為3 dBm 時，此接收機的最大轉換增益在3 GHz 的頻率為13.1 dB，整體的平均轉換增益約為3.5 dB。此接收機直流功耗為260 毫瓦，晶片面積則為2.16 mm2。

This dissertation presents the research and implementations on CMOS monotonic microwave integrated circuits (MMICs) and receiver integration of vital sign detection radar. The dissertation is categories into three parts: a wide-tuning-range dual-core VCO and a wideband phase-locked loop (PLL) front-end, a 90.9% locking range injection-locked frequency divider (ILFD), and a 2-to-30-GHz broadband receiver for vital sign detection. The dual-core VCO with switched inductors and varactor banks is introduced at the beginning. This VCO has been designed and fabricated in a standard 90-nm low-power CMOS technology. The proposed switched inductor changes the inductance of LC tank indirectly on the RF signal path, bringing minimum loading effect to the quality factor of resonator. The dual-core VCO demonstrates a tuning range of 62.1% (from 23.67 to 45 GHz). The average output power is around −11 dBm with the power consumption varying from 16 to 20 mW. The measured phase noise is −100.8 dBc/Hz at 1 MHz offset frequency operating at 23.67 GHz. By further combining the dual-core VCO with a divide-by-4 frequency divider, a wideband PLL front-end is implemented in the same CMOS process. The divide-by-4 frequency divider consists of a body-biasing injection-locked freqeucny divider (ILFD) stacked with source-injected current mode logic (SICML). This PLL front-end exhibits a frequency tuning range from 23.6 to 32 GHz (30.2%) with a chip size of 0.91 mm2. The dc power consumption is 40.8 mW at a supply voltages of 1.2 V and 1.5 V. Then, an ultra-wide-locking-range divide-by-2 ILFD in a standard 90-nm low-power CMOS technology is presented. The sizes of cross-coupled pair and injection mixer are optimized based on the device ratio to obtain a wide locking range at first. With the aid of inductive peaking, forward-body-bias, and harmonic suppression techniques, the proposed ILFD achieves a locking range of 90.9% (from 12 to 32 GHz) at injection power (Pinj ) = 0 dBm. The chip occupies an area of 0.45 mm2. Even with Pinj as low as −10 dBm, this ILFD maintains a locking range of 32.9%. The core dc power consumption is only 2.4 mW with a supply voltage of 0.6 V. Finally, a 2-to-30-GHz broadband receiver of the wideband vital sign detection radar is designed and fabricated in a 0.18-μm CMOS process. The aim of the wideband vital sign detection radar is using frequency diversity to maintain the detection accuracy under various detection environments. This 2-to-30-GHz receiver is composed of a high-gain low-noise distributed amplifier (DA) and a broadband down-conversion mixer, which is developed to cooperate with a dual-band transmitter. The proposed receiver achieves a fractional bandwidth of 175 %. The maximum conversion gain of the receiver is 13.1 dB at 3 GHz within a frequency range from 2 to 30 GHz at LO power of 3 dBm. The measured average conversion gain is around 3.5 dB. This receiver consumes a dc power of 260 mW and occupies a chip area of 2.16 mm2.

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