功率消耗限制下三維積體電路之記憶體內建自我測試設計及測試排程最佳化

3D IC Memory BIST Design and Test Scheduling under Power Constraints

10.6840/cycu201700349

柯妍君

三維積體電路 ； 記憶體測試排程 ； 內建自我測試 ； 3D ICs ； Memory Testing ； Built-in-self-test (BIST) ； Test Scheduling ； Test Application Time

中原大學電子工程學系學位論文

2017年

碩士

黃世旭

繁體中文

隨著系統晶片設計中嵌入式記憶體數量的增加，記憶體測試就會顯著地影響測試成本，所以記憶體測試技術中內建自我測試則成為主流，但是，三維積體電路中鮮少有文獻提及內建自我測試相關問題。不同於二維系統晶片，三維積體電路中包含了堆疊前測試與堆疊後測試，因此，每一階層可能需要額外的內建自我測試控制器來減少整體測試時間。此篇論文中，我們提出兩階段啟發式演算法，第一階段為距離限制之下將記憶體分群並分配內建自我測試控制器，第二階段則為功率消耗限制下進行測試排程。與過去的文獻相較之下，我們的方法能有效減少整體測試時間以及內建自我測試的面積。

With the increasing number of embedded memory cores in modern electronic system designs, the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective approach for memory testing. However, memory BIST for three-dimensional integrated circuits (3D ICs) has not been well studied. Different from 2D SOCs, the testing of 3D ICs consists of both pre-bond testing and post-bond testing. Therefore, extra memory BIST controllers may be required for each layer to reduce the total test application time. In this thesis, we propose a two-stage approach: the first stage performs memory grouping under distance constraints and the second stage performs test scheduling under power constraints. Compared to the previous work, our approach can improve both BIST area cost and total test time simultaneously.

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