功率消耗與測試墊限制下之三維積體電路測試排程問題研究

3D IC Test Scheduling under Power and Test Pads Constraints

10.6840/cycu201600695

許銘軒

三維積體電路 ； 測試排程 ； 測試墊 ； TAM Bus分配。 ； Three-dimensional (3D) integrated circuit (IC) ； test Scheduling ； test pads ； test time ； test access mechanism (TAM) bus assignment.

中原大學電子工程學系學位論文

2016年

碩士

黃世旭

繁體中文

隨著晶片的設計越來越複雜，三維積體電路(Three-Dimensional Integrated Circuits, 3D ICs)逐漸變成一種設計趨勢；然而在測試三維積體電路方面也相較於傳統電路複雜。與傳統的系統晶片測試相同，三維積體電路的功能核心會經由TAM Bus連接至外部測試機台(ATE)來做測試，不過在3D IC中，測試會分成兩個部分:pre-bond與post-bond測試，因此TAM Bus的分配與測試墊(Test Pad)的運用會更加複雜。因此在測試墊的數目與功率消耗限制下，如何有效運用TAM Bus分配以最小化整體測試排程的時間是我們研究目標。 在本篇文章中，我們提出整數線性規劃(Integer Linear Programming)方法來達到在功率消耗與測試墊數目的限制下，最小化整體測試時間。與過去的文獻比較，我們的方法能更有效的減少測試墊的數目並且同時最小化三維積體電路整體測試時間。

As the system-on-chip (SoC) design complexity continue to increase, three-dimensional integrated circuit (3D IC) design has become an industry trend. However, the testing of a 3D IC is more difficult than the testing of a 2D IC. As the same as a 2D IC, the core of a 3D IC must use the TAM Bus to connect with the automatic test equipment (ATE). But in for a 3D IC, its testing includes two parts: pre-bond testing and post-bond testing. The decision on the assignment of test access mechanism (TAM) Bus and the number of test pads of each layer becomes more complicated. Thus, our objective is to minimize the total test time of the 3D IC under the constraints on power consumption and the constraints on the number of test pad. In this thesis, we propose an integer linear programming (ILP) approach to perform the 3D IC test scheduling under test pads and peak power constraints. Different from previous works, our approach can minimize both test application time and the number of required test pads. Experimental results show that our approach achieves better results than previous works.

1. [1] Millican, Spencer K., and Kewal K. Saluja. "A test partitioning technique for scheduling tests for thermally constrained 3D integrated circuits." 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems. IEEE, 2014.
   連結：
2. [2] K. Shen, D. Xiang and Z. Jiang, “Dual-Speed TAM Optimization of 3D SoCs for Mid-bond and Post-bond Testing”, Proc. of IEEE ATS, pp. 7-12, 2014.
   連結：
3. [3] L. Jiang, et al., “Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3D SoCs under Pre-Bond Test-Pin-Count Constraint”, IEEE Trans. on VLSI Systems, vol. 20, no. 9, 2012.
   連結：
4. [4] L. Jiang, H. Lin and X. Qiang, “Test Architecture Design and Optimization for Three-Dimensional SoCs”, Proc. of IEEE DATE, pp. 220-225, 2009.
   連結：
5. [5] S.K. Millican and Kewal K. Saluja, “Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits”, Prof. of IEEE ATS, pp. 37-42, 2012.
   連結：
6. [6] Yao, Chunhua, Kewal K. Saluja, and Parameswaran Ramanathan. "Temperature dependent test scheduling for multi-core system-on-chip." Test Symposium (ATS), 2011 20th Asian. IEEE, 2011.
   連結：
7. [8] Yu, Thomas Edison, et al. "Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints." Proceedings of the 2009 Asia and South Pacific Design Automation Conference. IEEE Press, 2009.
   連結：
8. [9] He, Zhiyuan, Zebo Peng, and Petru Eles. "A heuristic for thermal-safe SoC test scheduling." Test Conference, 2007. ITC 2007. IEEE International. IEEE, 2007.
   連結：
9. [11] Vinay, N. S., et al. "Thermal aware test scheduling for stacked multi-chip-modules." Design & Test Symposium (EWDTS), 2010 East-West. IEEE, 2010.
   連結：
10. [13] SenGupta, Breeta, Urban Ingelsson, and Erik Larsson. "Scheduling tests for 3D stacked chips under power constraints." Journal of electronic testing 28.1 (2012): 121-135.
    連結：
11. [14] Marinissen, Erik Jan, and Yervant Zorian. "Testing 3D chips containing through-silicon vias." 2009 International Test Conference. IEEE, 2009.
    連結：
12. [15] Zhou, Lili, Cherry Wakayama, and C-J. Richard Shi. "Cascade: A standard supercell design methodology with congestion-driven placement for three-dimensional interconnect-heavy very large-scale integrated circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26.7 (2007): 1270-1282.
    連結：
13. [17] C. Yao, K. Saluja, P. Ramanathan, “Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies”, Asian Test Symposium, November 2009.
    連結：
14. [18] C.P. Xu, H.B. Hu, and J.H. Niu, “Test Scheduling of SOC with Power Constraint Based on Particle Swarm Optimization Algorithm”, Proc. of IEEE International Conference on Genetic and Evolutionary Computing, pp. 611—614, 2009.
    連結：
15. [19] Marinissen, Erik Jan, Sandeep Kumar Goel, and Maurice Lousberg. "Wrapper design for embedded core test." Test Conference, 2000. Proceedings. International. IEEE, 2000.
    連結：
16. [20] Higgins, Michael, Ciaran MacNamee, and Brendan Mullane. "IEEE 1500 wrapper control using an IEEE 1149.1 test access port." Signals and Systems Conference, 208.(ISSC 2008). IET Irish. IET, 2008.
    連結：
17. [21] Millican, Spencer K., and Kewal K. Saluja. "Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints." 2015 28th International Conference on VLSI Design. IEEE, 2015.
    連結：
18. [22] He, Zhiyuan, et al. "Thermal-aware SoC test scheduling with test set partitioning and interleaving." Journal of electronic testing 24.1-3 (2008): 247-257.
    連結：
19. [23] Hsu, Huan-Shan, et al. "Test scheduling and test access architecture optimization for system-on-Chip." Test Symposium, 2002.(ATS'02). Proceedings of the 11th Asian. IEEE, 2002.
    連結：
20. [24] He, Zhiyuan, et al. "Power-constrained hybrid BIST test scheduling in an abort-on-first-fail test environment." 8th Euromicro Conference on Digital System Design (DSD'05). IEEE, 2005.
    連結：
21. [25] Larsson, Erik, and Hideo Fujiwara. "System-on-chip test scheduling with reconfigurable core wrappers." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14.3 (2006): 305-309.
    連結：
22. [26] Lee, Hsien-Hsin S., and Krishnendu Chakrabarty. "Test challenges for 3D integrated circuits." IEEE Design & Test of Computers 26.5 (2009): 26-35.
    連結：
23. [27] Wu, X., Chen, Y., Chakrabarty, K., & Xie, Y. (2010). "Test-access mechanism optimization for core-based three-dimensional SOCs". Microelectronics Journal, 41(10), 601-615.
    連結：
24. [28] Fukushima, Takafumi, et al. "New three-dimensional integration technology using chip-to-wafer bonding to achieve ultimate super-chip integration." Japanese journal of applied physics 45.4S (2006): 3030.
    連結：
25. [29] Xu, Q., & Nicolici, N. (2004). "Multi-frequency test access mechanism design for modular SOC testing". In Asian test symposium (pp. 2-7).
    連結：
26. [30] Lee, Hsien-Hsin S., and Krishnendu Chakrabarty. "Test challenges for 3D integrated circuits." IEEE Design & Test of Computers 26.5 (2009): 26-35.
    連結：
27. [31] Ming-Hsuan Hsu, Chun-Hua Cheng, Shih-Hsu Huang. "3D IC test scheduling with test pads considered." International Symposium on Next-Generation Electronics (ISNE), 4-6 May 2016, (pp. 1-2)
    連結：
28. [32] S.H. Huang, C.H. Chiu, C.H. Cheng, T.J. Wang, "Simultaneous Test Scheduling and TAM Bus Wire Assignment for Temperature-Dependent Core-Based SoC Testing ", International Journal of Electrical Engineering (IJEE), vol. 23, no. 4, pp. 53-62, 2016.
    連結：
29. [7] Yao, C., Saluja, K. K., & Ramanathan, P. (2011). Power and thermal constrained test scheduling under deep submicron technologies. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 30(2), 317-322.
30. [10] Rosinger, Paul, Bashir M. Al-Hashimi, and Krishnendu Chakrabarty. "Thermal-safe test scheduling for core-based system-on-chip integrated circuits." Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 25.11 (2006).
31. [12] Roy, Sandip Kumar, et al. "Session Based Core Test Scheduling for 3D SOCs." VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on. IEEE, 2014.
32. [16] Marinissen, Erik Jan, Vikram Iyengar, and Krishnendu Chakrabarty. "A set of benchmarks for modular testing of SOCs." Test Conference, 2002. Proceedings. International. IEEE, 2002.