三維晶片封裝可靠度負載對於奈米元件效能影響之研究

Reliability loading impacts of 3D-ICs package on the influence investigation of Nanoscaled device performance.

10.6840/cycu201600478

陳建勳

三維晶片封裝 ； 矽穿孔 ； 殘留應力 ； 應變工程技術 ； 有限元素法 ； 3D-ICs packaging ； Through Silicon Via (TSV) ； Residual stress ； Strain engineering technology ； Finite element method

中原大學機械工程學系學位論文

2016年

碩士

李昌駿

繁體中文

1971年，Gorden Moore所提出的莫爾定律支配了半導體領域長達44年之久，然而近期，英特爾公司的執行長Brian Krzanich 對外宣佈產品的更新週期已延長至2年半，這意味著對眾多半導體企業而言，莫爾定律中提出的兩年內積體電路效能提升一倍的理論已無法適用於下一世代的製程中。當平面式場效電晶體的結構無法更有效的縮減尺寸時，三維晶片堆疊技術可以增加單位面積下的電晶體密度。藉由晶片堆疊技術，在固定區域內的電晶體數量可以有效的提升，而隨著三維晶片堆疊技術，矽穿孔結構為上下晶片傳遞訊號的重要結構。 在本研究中，矽穿孔周圍之場效電晶體元件受矽穿孔殘留拉伸應力的影響將被討論。此殘留應力在矽穿孔製程中發生，在理想情況下銅熱膨脹對周邊矽基板造成壓應力，然而在真實情況下銅柱在高溫下會產生塑性應變，以致於對周圍矽基板的壓應力藉由變形釋放掉。而在冷卻時銅晶格產生強力內縮行為，這也是銅柱內部拉伸應力的來源。本研究中亦討論應變工程技術的影響，在應變工程技術中，將鍺或碳原子以矽鍺、矽碳合金的形式磊晶成長於源汲極處，並藉由晶格常數不匹配的特性進而對載子通道產生壓縮或拉伸應力。通過應變工程技術，可明顯的增加場效電晶體的載子遷移率。溫度負載以及場效電晶體設置位置的影響也在研究中被一同討論。本研究中採用有限元素分析法(FEM)來分析通道內的應力分佈，並使用壓阻係數方程式計算電晶體元件的載子遷移率增量。 在模擬結果中，矽穿孔殘留拉伸應力可增加N型電晶體的載子遷移率。矽穿孔直徑為30μm且殘留應力為700MPa拉伸應力時，N型電晶體提升5.4%的載子遷移率，在同樣的條件下P型電晶體的電洞載子遷移率則下降3%。當電晶體元件的位置改變時，載子遷移率也有所變化；考慮在相同的條件下並改變電晶體位置後，N型場效電晶體載子遷移率會上升7% 而P型電晶體則下降25%。藉由模擬結果，矽穿孔殘留應力與電晶體元件設置位置的影響將於本研究中被討論。

In 1971, Gordon Moore had proposed the Moore's law which predicted the developing of integrated circuit in 44 years. However, the Intel CEO Brian Krzanich has announced that the performance improvements update cycle has extend to two and half years in the near term. It means that the Moore's law for semiconductor industry is not suitable for next generation devices. When the structure geometry of planar type metal oxide semiconductor field transistor (MOSFET) cannot reduce efficiently, one way to increase the transistor density was introduced by three dimensional chips stacking technology. By using the chip stacking technology, transistor density in fixed region can be improved significantly. In three dimensional chips stacking technology, the key point of signal transmission on stacked chips is through silicon via (TSV) structure. In this research, the mobility gain of MOSFET which affected by TSV residual tensile stress has been discussed. TSV residual stress appeared during the TSV manufacture process. In the ideal situation, TSV has induced compressive stress which is induced by the coefficient of thermal expansion mismatch between TSV copper and silicon interposer. However in the true situation, TSV structure appeared tensile stress. The TSV residual tensile stress has been considered in this research. Strain engineering technology has been discussed in this research too. In strain engineering technology, germanium or carbon lattice is doped in the source/drain region. By the effect of lattice coefficient mismatch, SiGe or SiC lattice can induce compressive or tensile stress in silicon channel. By using strain engineering technology, MOSFET' carrier mobility has increased and enhance electronic performance. In this research, the influence of temperature loading and the influence of MOSFET position in packaging structure has be considered. Finite element method (FEM) is used to analysis MOSFET channel stress distribution in this research. Furthermore, using piezoresistive coefficient equation, MOSFET mobility gain can be calculate. In simulation result, TSV residual tensile stress has increased N-type MOSFET mobility gain. When TSV diameter is 30μm and TSV residual stress has 700MPa tensile stress the N-type MOSFET mobility will increase 5.4%. At the same situation, PMOSFET’s hole carrier mobility has decreased 3%. When the MOSFET position has change in another region, carrier mobility will be change；consider the MOSFET has the same residual stress effect (TSV diameter is 30μm, residual stress is 700MPa ), NMOSFET’s mobility has increased 7% and PMOSFET has decreased 25%. By the simulation result, influences of TSV residual stress and MOSFET position has discussed in this research.

1. [1]R. A. Robison, “Moore's Law: predictor and driver of the silicon era,” World neurosurgery, vol. 78, no. 5, pp. 399-403, 2012.
   連結：
2. [2]K. Tu, “Reliability challenges in 3D IC packaging technology,” Microelectronics Reliability, vol. 51, no. 3, pp. 517-523, 2011.
   連結：
3. [3]J. U. Knickerbocker, C. S. Patel, P. S. Andry, C. K. Tsang, L. P. Buchwalter, E. J. Sprogis, H. Gan, R. R. Horton, R. J. Polastre, and S. L. Wright, “3-D silicon integration and silicon packaging technology using silicon through-vias,” Solid-State Circuits, IEEE Journal of, vol. 41, no. 8, pp. 1718-1725, 2006.
   連結：
4. [5]S. C. Hong, W. G. Lee, W. J. Kim, J. H. Kim, and J. P. Jung, “Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking,” Microelectronics Reliability, vol. 51, no. 12, pp. 2228-2235, 2011.
   連結：
5. [7]M. Song, L. Chen, and J. A. Szpunar, “Thermomechanical Characteristics of Copper Through-Silicon via Structures,” Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 5, no. 2, pp. 225-231, 2015.
   連結：
6. [8]S. Seta, and S. Shimizu, “Mechanism of microtrench generation in etching of wiring trench on SiO2 layer: Proposal of simulation model using high-pressure etching gas,” Japanese journal of applied physics, vol. 46, no. 6R, pp. 3589, 2007.
   連結：
7. [9]S. D. Suk, S.-Y. Lee, S.-M. Kim, E.-J. Yoon, M.-S. Kim, M. Li, C. W. Oh, K. H. Yeo, S. H. Kim, and D.-S. Shin, “High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability,” IEDM Tech. Dig, pp. 717-720, 2005.
   連結：
8. [10]C.-C. Lee, C.-H. Liu, H.-W. Hsu, and M.-H. Hung, “Effects of extended poly gate on the performance of strained P-type metal-oxide-semiconductor field-effect transistors with a narrow channel width,” Thin Solid Films, vol. 557, pp. 311-315, 2014.
   連結：
9. [11]S. S. Sylvia, H.-H. Park, M. A. Khayer, K. Alam, G. Klimeck, and R. K. Lake, “Material selection for minimizing direct tunneling in nanowire transistors,” Electron Devices, IEEE Transactions on, vol. 59, no. 8, pp. 2064-2069, 2012.
   連結：
10. [12]S. Thompson, S. Suthram, Y. Sun, G. Sun, S. Parthasarathy, M. Chu, and T. Nishida, "Future of strained Si/semiconductors in nanoscale MOSFETs." pp. 1-4.
    連結：
11. [13]S. Gupta, V. Moroz, L. Smith, Q. Lu, and K. C. Saraswat, “7-nm FinFET CMOS design enabled by stress engineering using Si, Ge, and Sn,” Electron Devices, IEEE Transactions on, vol. 61, no. 5, pp. 1222-1230, 2014.
    連結：
12. [14]N. Serra, and D. Esseni, “Mobility Enhancement in Strained-FinFETs: Basic Insight and Stress Engineering,” Electron Devices, IEEE Transactions on, vol. 57, no. 2, pp. 482-490, 2010.
    連結：
13. [15]Y. Ding, R. Cheng, S.-M. Koh, B. Liu, and Y.-C. Yeo, “Phase change liner stressor for strain engineering of p-channel FinFETs,” Electron Devices, IEEE Transactions on, vol. 60, no. 9, pp. 2703-2711, 2013.
    連結：
14. [16]F. Conzatti, N. Serra, D. Esseni, M. De Michielis, A. Paussa, P. Palestri, L. Selmi, S. M. Thomas, T. E. Whall, and D. Leadley, “Investigation of strain engineering in FinFETs comprising experimental analysis and numerical simulations,” Electron Devices, IEEE Transactions on, vol. 58, no. 6, pp. 1583-1593, 2011.
    連結：
15. [17]D. Zhang, B. Nguyen, T. White, B. Goolsby, T. Nguyen, V. Dhandapani, J. Hildreth, M. Foisy, V. Adams, and Y. Shiho, "Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement." pp. 26-27.
    連結：
16. [19]W.-S. Liao, Y.-G. Liaw, M.-C. Tang, K.-M. Chen, S.-Y. Huang, C.-Y. Peng, and C. W. Liu, “PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD-SiN x Stressing Layer,” Electron Device Letters, IEEE, vol. 29, no. 1, pp. 86-88, 2008.
    連結：
17. [20]C.-C. Lee, C.-H. Liu, and H.-H. Teng, “Simulation-based sensitivity estimation of the geometric effect of poly gates on nanoscale n-type metal-oxide-semiconductor field-effect transistors with silicon–carbon alloy,” Thin Solid Films, vol. 570, pp. 336-342, 2014.
    連結：
18. [21]K.-W. Ang, K.-J. Chui, V. Bliznetsov, Y. Wang, L.-Y. Wong, C.-H. Tung, N. Balasubramanian, M.-F. Li, G. Samudra, and Y.-C. Yeo, "Thin body silicon-on-insulator N-MOSFET with silicon-carbon source/drain regions for performance enhancement." pp. 497-500.
    連結：
19. [22]C. S. Selvanayagam, J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. Chai, “Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps,” Advanced Packaging, IEEE Transactions on, vol. 32, no. 4, pp. 720-728, 2009.
    連結：
20. [23]E. Cheng, and Y.-L. Shen, “Thermal expansion behavior of through-silicon-via structures in three-dimensional microelectronic packaging,” Microelectronics Reliability, vol. 52, no. 3, pp. 534-540, 2012.
    連結：
21. [25]W. Feng, N. Watanabe, H. Shimamoto, M. Aoyagi, and K. Kikuchi, “Validation of TSV thermo-mechanical simulation by stress measurement,” Microelectronics Reliability, 2016.
    連結：
22. [27]A. Budiman, H.-A.-S. Shin, B.-J. Kim, S.-H. Hwang, H.-Y. Son, M.-S. Suh, Q.-H. Chung, K.-Y. Byun, N. Tamura, and M. Kunz, “Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits,” Microelectronics Reliability, vol. 52, no. 3, pp. 530-533, 2012.
    連結：
23. [28]B.-J. Kim, J.-H. Kim, S.-H. Hwang, A. S. Budiman, H.-Y. Son, K.-Y. Byun, N. Tamura, M. Kunz, D.-I. Kim, and Y.-C. Joo, “Microstructure evolution and defect formation in Cu through-silicon vias (TSVs) during thermal annealing,” Journal of electronic materials, vol. 41, no. 4, pp. 712-719, 2012.
    連結：
24. [29]G. Wang, G. Ding, R. Liu, J. Luo, D. Niu, J. Zhao, X. Zhao, and Y. Wang, “Design, simulation and fabrication of a flexible bond pad with a hollow annular protuberance to improve the thermal fatigue lifetime for through-silicon vias,” Journal of Micromechanics and Microengineering, vol. 24, no. 12, pp. 125017, 2014.
    連結：
25. [30]Q. Chen, C. Huang, D. Wu, Z. Tan, and Z. Wang, “Ultralow-capacitance through-silicon vias with annular air-gap insulation layers,” Electron Devices, IEEE Transactions on, vol. 60, no. 4, pp. 1421-1426, 2013.
    連結：
26. [31]X. Yin, Z. Zhu, Y. Yang, and R. Ding, “Metal Proportion Optimization of Annular Through-Silicon via Considering Temperature and Keep-Out Zone,” Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 5, no. 8, pp. 1093-1099, 2015.
    連結：
27. [32]F. Wang, Z. Zhu, Y. Yang, X. Yin, X. Liu, and R. Ding, “An effective approach of reducing the keep-out-zone induced by coaxial through-silicon-via,” Electron Devices, IEEE Transactions on, vol. 61, no. 8, pp. 2928-2934, 2014.
    連結：
28. [33]F. Wang, Z. Zhu, Y. Yang, X. Liu, and R. Ding, “Analytical models for the thermal strain and stress induced by annular through-silicon-via (TSV),” IEICE Electronics Express, vol. 10, no. 20, pp. 20130666-20130666, 2013.
    連結：
29. [34]F. Wang, and N. Yu, “Study on thermal stress and keep-out zone induced by Cu and SiO 2 filled coaxial-annular through-silicon via,” IEICE Electronics Express, no. 0, 2015.
    連結：
30. [35]L. Filipovic, A. P. Singulani, F. Roger, S. Carniello, and S. Selberherr, “Intrinsic stress analysis of tungsten-lined open TSVs,” Microelectronics Reliability, vol. 55, no. 9, pp. 1843-1848, 2015
    連結：
31. [36]L. Filipovic, and S. Selberherr, “The effects of etching and deposition on the performance and stress evolution of open through silicon vias,” Microelectronics Reliability, vol. 54, no. 9, pp. 1953-1958, 2014.
    連結：
32. [37]M. Liao, “The reduction of keep-out zone (∼ 10×) by the optimized novel trench structures near the through silicon vias for the application in 3-dimensional integrated circuits,” Journal of Applied Physics, vol. 114, no. 15, pp. 153515, 2013.
    連結：
33. [39]F. M. Bufler, A. Erlebach, and M. Oulmane, “Hole mobility model with silicon inversion layer symmetry and stress-dependent piezoconductance coefficients,” Electron Device Letters, IEEE, vol. 30, no. 9, pp. 996-998, 2009.
    連結：
34. [41]C. Okoro, L. E. Levine, R. Xu, K. Hummler, and Y. S. Obeng, “Nondestructive measurement of the residual stresses in copper through-silicon vias using synchrotron-based microbeam X-ray diffraction,” Electron Devices, IEEE Transactions on, vol. 61, no. 7, pp. 2473-2479, 2014.
    連結：
35. [42]M. Knaut, M. Junige, V. Neumann, H. Wojcik, T. Henke, C. Hossbach, A. Hiess, M. Albert, and J. W. Bartha, “Atomic layer deposition for high aspect ratio through silicon vias,” Microelectronic Engineering, vol. 107, pp. 80-83, 2013.
    連結：
36. [43]C.-C. Lee, Y.-M. Lin, Y.-H. Guo, C.-J. Zhan, T.-C. Chang, and Y.-H. Dzeng, “Assembly reliability improvement of 3D-ICs packaging using pre-stuffed molding material,” Vacuum, vol. 118, pp. 152-160, 2015.
    連結：
37. [44]C.-C. Lee, C.-P. Hsieh, M.-H. Liao, S.-W. Cheng, and Y.-H. Guo, "Effects of array type of dummy active diffused region and gate geometries on narrow NMOSFETs with SiC S/D stressors." pp. 1-4.
    連結：
38. [4]N. Khan, V. S. Rao, S. Lim, H. S. We, V. Lee, X. Zhang, E. Liao, R. Nagarajan, T. Chai, and V. Kripesh, “Development of 3-D silicon module with TSV for system in packaging,” Components and Packaging Technologies, IEEE Transactions on, vol. 33, no. 1, pp. 3-9, 2010.
39. [6]N. Ranganathan, D. Y. Lee, L. Youhe, G.-Q. Lo, K. Prasad, and K. L. Pey, “Influence of Bosch etch process on electrical isolation of TSV structures,” Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 1, no. 10, pp. 1497-1507, 2011.
40. [18]S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, and B. Mcintyre, “A logic nanotechnology featuring strained-silicon,” Electron Device Letters, IEEE, vol. 25, no. 4, pp. 191-193, 2004.
41. [24]C. Selvanayagam, X. Zhang, R. Rajoo, and D. Pinjala, “Modeling stress in silicon with TSVs and its effect on mobility,” Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 1, no. 9, pp. 1328-1335, 2011.
42. [26]I. De Wolf, K. Croes, O. V. Pedreira, R. Labie, A. Redolfi, M. Van De Peer, K. Vanstreels, C. Okoro, B. Vandevelde, and E. Beyne, “Cu pumping in TSVs: Effect of pre-CMP thermal budget,” Microelectronics Reliability, vol. 51, no. 9, pp. 1856-1859, 2011.
43. [38]劉思科, 朱秉升, 羅普生, "半導體物理學," 電子工業出版社, 2006.
44. [40]S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, and T. Hoffman, “A 90-nm logic technology featuring strained-silicon,” Electron Devices, IEEE Transactions on, vol. 51, no. 11, pp. 1790-1797, 2004.