三維積體電路關鍵技術與異質接合製程平台之電性與可靠度研究

Development, Electrical Performance, and Reliability Investigations of 3-D ICs Key Technologies and Hybrid Bonding Process Platform

張耀仁

三維積體電路 ； 混和接合 ； 矽晶直通孔 ； 3DIC ； Hybrid bonding ； TSV

交通大學電子工程系所學位論文

2016年

博士

陳冠能

英文

1. [1] H.-S. Wong, “Beyond the conventional transistor,” IBM Journal of Research and Development, vol. 46, no. 2.3, pp. 133-168, 2002.
   連結：
2. [2] V. Agarwal, M. Hrishikesh, S. W. Keckler, and D. Burger, Clock rate versus IPC: The end of the road for conventional microarchitectures: ACM, 2000.
   連結：
3. [4] G. G. Shahidi, "SOI technology for the GHz era." pp. 11-14.
   連結：
4. [5] M. Ieong, J. Kedzierski, Z. Ren, B. Doris, T. Kanarsky, and H.-S. Wong, “Ultra-thin silicon channel single-and double-gate MOSFETs,” SOLID STATE DEVICES AND MATERIALS, pp. 136-137, 2002.
   連結：
5. [6] J.-T. Park, and J.-P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines,” Electron Devices, IEEE Transactions on, vol. 49, no. 12, pp. 2222-2229, 2002.
   連結：
6. [7] K. Rim, J. Chu, H. Chen, K. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, and J. Newbury, "Characteristics and device design of sub-100 nm strained Si N-and PMOSFETs." pp. 98-99.
   連結：
7. [9] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, and K. Asano, "Sub 50-nm finfet: Pmos." pp. 67-70.
   連結：
8. [13] "Semiconductor Industry Association, International Technology Roadmap for Semiconductors," http:// www.itrs.net/Common/2004Update/2004Update.htm.
   連結：
9. [14] K. Guarini, A. Topol, M. Ieong, R. Yu, L. Shi, M. Newport, D. Frank, D. Singh, G. Cohen, and S. Nitta, "Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication." pp. 943-945.
   連結：
10. [16] Y. Uemoto, E. Fujii, A. Nakamura, and K. Senda, "A high-performance stacked-CMOS SRAM cell by solid phase growth technique." pp. 21-22.
    連結：
11. [17] T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto, "Three dimensional ICs, having four stacked active device layers." pp. 837-840.
    連結：
12. [18] D. J. Frank, "Power-constrained device and technology design for the end of scaling." pp. 643-646.
    連結：
13. [22] S. Jagar, M. Chan, M. Poon, H. Wang, M. Qin, P. K. Ko, and Y. Wang, "Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization." pp. 293-296.
    連結：
14. [23] S. Pae, T. Su, J. P. Denton, and G. W. Neudeck, “Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth,” Electron Device Letters, IEEE, vol. 20, no. 5, pp. 194-196, 1999.
    連結：
15. [24] L. Xue, C. Liu, and S. Tiwari, "Multi-layers with buried structures (mlbs): An approach to three-dimensional integration." pp. 117-118.
    連結：
16. [25] V. W. Chan, P. C. Chan, and M. Chan, “Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization,” Electron Devices, IEEE Transactions on, vol. 48, no. 7, pp. 1394-1399, 2001.
    連結：
17. [26] A. W. Topol, B. K. Furman, K. W. Guarini, L. Shi, G. M. Cohen, and G. F. Walker, "Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures." pp. 931-938.
    連結：
18. [27] P. Morrow, C.-M. Park, S. Ramanathan, M. Kobrinsky, and M. Harmes, “Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology,” Electron Device Letters, IEEE, vol. 27, no. 5, pp. 335-337, 2006.
    連結：
19. [28] K. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. Park, H. Kurino, and M. Koyanagi, "Three-dimensional shared memory fabricated using wafer stacking technology." pp. 165-168.
    連結：
20. [29] A. W. Topol, D. La Tulipe, L. Shi, S. Alam, D. Frank, S. Steen, J. Vichiconti, D. Posillico, M. Cobb, and S. Medd, "Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)." pp. 352-355.
    連結：
21. [32] S. Oktyabrsky, J. Castracane, and A. E. Kaloyeros, "Emerging technologies for chip-level optical interconnects." pp. 213-224.
    連結：
22. [33] B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens, S. Stoukatch, D. S. Tezcan, and Z. Tokei, "3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias." pp. 1-4.
    連結：
23. [34] F. Liu, R. Yu, A. Young, J. Doyle, X. Wang, L. Shi, K. Chen, X. Li, D. Dipaola, and D. Brown, "A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding." pp. 1-4.
    連結：
24. [36] M. Umemoto, K. Tanida, Y. Nemoto, M. Hoshino, K. Kojima, Y. Shirai, and K. Takahashi, "High-performance vertical interconnection for high-density 3D chip stacking package." pp. 616-623.
    連結：
25. [37] A. Jourdain, S. Stoukatch, P. De Moor, and W. Ruythooren, "Simultaneous Cu-Cu and compliant dielectric bonding for 3D stacking of ICs." pp. 207-209.
    連結：
26. [38] A. Jourdain, P. Soussan, B. Swinnen, and E. Beyne, "Electrically yielding collective hybrid bonding for 3D stacking of ICs." pp. 11-13.
    連結：
27. [41] C.-J. Zhan, J.-Y. Juang, Y.-M. Lin, Y.-W. Huang, K.-S. Kao, T.-F. Yang, S.-T. Lu, J. H. Lau, T.-H. Chen, and R. Lo, "Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization." pp. 14-21.
    連結：
28. [44] P. Svasek, E. Svasek, B. Lendl, and M. Vellekoop, “Fabrication of miniaturized fluidic devices using SU-8 based lithography and low temperature wafer bonding,” Sensors and Actuators A: Physical, vol. 115, no. 2, pp. 591-599, 2004.
    連結：
29. [45] P. Abgrall, C. Lattes, V. Conédéra, X. Dollat, S. Colin, and A. M. Gué, “A novel fabrication method of flexible and monolithic 3D microfluidic structures using lamination of SU-8 films,” Journal of Micromechanics and Microengineering, vol. 16, pp. 113, 2006.
    連結：
30. [47] S. Bader, W. Gust, and H. Hieber, “Rapid formation of intermetallic compounds interdiffusion in the Cu---Sn and Ni---Sn systems,” Acta metallurgica et materialia, vol. 43, no. 1, pp. 329-337, 1995.
    連結：
31. [48] R. Agarwal, W. Zhang, P. Limaye, and W. Ruythooren, "High density Cu-Sn TLP bonding for 3D integration." pp. 345-349.
    連結：
32. [49] H. Liu, K. Wang, K. Aasmundtveit, and N. Hoivik, “Intermetallic Compound Formation Mechanisms for Cu-Sn Solid–Liquid Interdiffusion Bonding,” Journal of Electronic Materials, pp. 1-10, 2012.
    連結：
33. [50] L. Li, J. Jiao, L. Luo, and Y. Wang, "Cu/Sn isothermal solidification technology for hermetic packaging of MEMS." pp. 1133-1137.
    連結：
34. [52] R. Reif, A. Fan, K. N. Chen, and S. Das, "Fabrication technologies for three-dimensional integrated circuits." pp. 33-37.
    連結：
35. [53] F. Bartels, J. Morris, G. Dalke, and W. Gust, “Intermetallic phase formation in thin solid-liquid diffusion couples,” Journal of Electronic Materials, vol. 23, no. 8, pp. 787-790, 1994.
    連結：
36. [54] Y. Rong, J. Cai, S. Wang, and S. Jia, "Low temperature Cu-Sn bonding by isothermal solidification technology." pp. 96-98.
    連結：
37. [56] A. W. Topol, D. La Tulipe, L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, and K. W. Guarini, “Three-dimensional integrated circuits,” IBM Journal of Research and Development, vol. 50, no. 4.5, pp. 491-506, 2006.
    連結：
38. [57] R. S. Patti, “Three-dimensional integrated circuits and the future of system-on-chip designs,” Proceedings of the IEEE, vol. 94, no. 6, pp. 1214-1224, 2006.
    連結：
39. [60] T. Fukushima, H. Kikuchi, Y. Yamada, T. Konno, J. Liang, K. Sasaki, K. Inamura, T. Tanaka, and M. Koyanagi, "New three-dimensional integration technology using self-assembly technique."
    連結：
40. [61] J. McMahon, E. Chan, S. Lee, R. Gutmann, and J.-Q. Lu, "Bonding interfaces in wafer-level metal/adhesive bonded 3D integration." pp. 871-878.
    連結：
41. [62] K.-N. Chen, S. H. Lee, P. S. Andry, C. K. Tsang, A. W. Topol, Y.-M. Lin, J.-Q. Lu, A. M. Young, M. Ieong, and W. Haensch, "Structure, design and process control for Cu bonded interconnects in 3D integrated circuits." pp. 1-4.
    連結：
42. [63] C.-K. Lee, T.-C. Chang, Y.-J. Huang, H.-C. Fu, J.-H. Huang, Z.-C. Hsiao, J. H. Lau, C.-T. Ko, R.-S. Cheng, and P.-C. Chang, "Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration." pp. 1468-1474.
    連結：
43. [64] C.-T. Ko, and K.-N. Chen, “Wafer-level bonding/stacking technology for 3D integration,” Microelectronics reliability, vol. 50, no. 4, pp. 481-488, 2010.
    連結：
44. [66] K. Takahashi, and M. Sekiguchi, "Through silicon via and 3-D wafer/chip stacking technology." pp. 89-92.
    連結：
45. [69] P. Coudrain, P. Magnan, P. Batude, X. Gagnard, C. Leyris, M. Vinet, A. Castex, C. Lagahe-Blanchard, A. Pouydebasque, and Y. Cazaux, “Investigation of a sequential three-dimensional process for back-illuminated CMOS image sensors with miniaturized pixels,” Electron Devices, IEEE Transactions on, vol. 56, no. 11, pp. 2403-2413, 2009.
    連結：
46. [72] J.-S. Kim, C. S. Oh, H. Lee, D. Lee, H. R. Hwang, S. Hwang, B. Na, J. Moon, J.-G. Kim, and H. Park, “A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 128 I/Os Using TSV Based Stacking,” Solid-State Circuits, IEEE Journal of, vol. 47, no. 1, pp. 107-116, 2012.
    連結：
47. [73] G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, “Electrical modeling and characterization of through silicon via for three-dimensional ICs,” Electron Devices, IEEE Transactions on, vol. 57, no. 1, pp. 256-262, 2010.
    連結：
48. [76] G. Katti, M. Stucchi, J. Van Olmen, K. De Meyer, and W. Dehaene, “Through-silicon-via capacitance reduction technique to benefit 3-D IC performance,” Electron Device Letters, IEEE, vol. 31, no. 6, pp. 549-551, 2010.
    連結：
49. [78] T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, and R. Tummala, "Electrical modeling of through silicon and package vias." pp. 1-8.
    連結：
50. [79] C. Xu, H. Li, R. Suaya, and K. Banerjee, “Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs,” Electron Devices, IEEE Transactions on, vol. 57, no. 12, pp. 3405-3417, 2010.
    連結：
51. [80] L. Zhang, L. Peng, H. Li, G. Lo, D. Kwong, and C. Tan, “Operating TSV in Stable Accumulation Capacitance Region by Utilizing-Induced Negative Fixed Charge,” Electron Device Letters, IEEE, vol. 33, no. 6, pp. 875-877, 2012.
    連結：
52. [81] L. Zhang, H. Li, S. Gao, and C. Tan, “Achieving stable through-silicon via (TSV) capacitance with oxide fixed charge,” Electron Device Letters, IEEE, vol. 32, no. 5, pp. 668-670, 2011.
    連結：
53. [82] Y.-J. Chang, C.-T. Ko, and K.-N. Chen, “Electrical and reliability investigation of Cu TSVs with low-temperature Cu/Sn and BCB hybrid bond scheme,” Electron Device Letters, IEEE, vol. 34, no. 1, pp. 102-104, 2013.
    連結：
54. [83] C.-T. Ko, Z.-C. Hsiao, Y.-J. Chang, P.-S. Chen, Y.-J. Hwang, H.-C. Fu, J.-H. Huang, C.-W. Chiang, S.-S. Sheu, and Y.-H. Chen, “A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application,” Device and Materials Reliability, IEEE Transactions on, vol. 12, no. 2, pp. 209-216, 2012.
    連結：
55. [84] Y.-J. Chang, C.-T. Ko, T.-H. Yu, C.-H. Chiang, and K.-N. Chen, “Backside-Process-Induced Junction Leakage and Process Improvement of Cu TSV Based on Cu/Sn and BCB Hybrid Bonding,” Electron Device Letters, IEEE, vol. 34, no. 3, pp. 435 - 437 2013.
    連結：
56. [85] L. Lima, J. Diniz, I. Doi, and J. Godoy Fo, “Titanium nitride as electrode for MOS technology and Schottky diode: Alternative extraction method of titanium nitride work function,” Microelectronic Engineering, vol. 92, pp. 86-90, 2012.
    連結：
57. [86] Y.-S. Tang, Y.-J. Chang, and K.-N. Chen, “Wafer-level Cu–Cu bonding technology,” Microelectronics Reliability, vol. 52, no. 2, pp. 312-320, 2012.
    連結：
58. [87] D. W. Kim, R. Vidhya, B. Henderson, U. Ray, S. Gu, W. Zhao, R. Radojcic, and M. Nowak, "Development of 3D through silicon stack (TSS) assembly for wide IO memory to logic devices integration." pp. 77-80.
    連結：
59. [88] B. Banijamali, S. Ramalingam, K. Nagarajan, and R. Chaware, "Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA." pp. 285-290.
    連結：
60. [89] B. T. Tung, F. Kato, N. Watanabe, S. Nemoto, K. Kikuchi, and M. Aoyagi, “15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications,” Japanese Journal of Applied Physics, vol. 53, no. 4S, pp. 04EB04, 2014.
    連結：
61. [90] D. Liu, and S. Park, “Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art,” Journal of Electronic Packaging, vol. 136, no. 1, pp. 014001, 2014.
    連結：
62. [92] B. Chao, S.-H. Chae, X. Zhang, K.-H. Lu, J. Im, and P. S. Ho, “Investigation of diffusion and electromigration parameters for Cu–Sn intermetallic compounds in Pb-free solders using simulated annealing,” Acta Materialia, vol. 55, no. 8, pp. 2805-2814, 2007.
    連結：
63. [93] J. Görlich, G. Schmitz, and K. Tu, “On the mechanism of the binary Cu/Sn solder reaction,” Applied Physics Letters, vol. 86, no. 5, pp. 053106, 2005.
    連結：
64. [94] R. Labie, W. Ruythooren, and J. Van Humbeeck, “Solid state diffusion in Cu–Sn and Ni–Sn diffusion couples with flip-chip scale dimensions,” Intermetallics, vol. 15, no. 3, pp. 396-403, 2007.
    連結：
65. [95] B. Lee, J. Park, J. Song, K.-w. Kwon, and H.-j. Lee, “Effects of bonding temperature and pressure on the electrical resistance of Cu/Sn/Cu joints for 3D integration applications,” Journal of Electronic Materials, vol. 40, no. 3, pp. 324-329, 2011.
    連結：
66. [96] C. W. Chang, S. C. Yang, C.-T. Tu, and C. R. Kao, “Cross-interaction between Ni and Cu across Sn layers with different thickness,” Journal of electronic materials, vol. 36, no. 11, pp. 1455-1461, 2007.
    連結：
67. [3] R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassous, and A. R. Leblanc, “Design of ion-implanted MOSFET's with very small physical dimensions,” Proceedings of the IEEE, vol. 87, no. 4, pp. 668-678, 1999.
68. [8] K. Guarini, P. Solomon, Y. Zhang, K. Chan, E. Jones, G. Cohen, A. Krasnoperova, M. Ronay, O. Dokumaci, and J. Bucchignano, "Triple-self-aligned, planar double-gate MOSFETs: devices and circuits." pp. 19.2. 1-19.2. 4.
69. [10] M. Alexe, and U. Gösele, Wafer bonding: applications and technology: Springer Science & Business Media, 2013.
70. [11] J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif, and J. D. Meindl, “Interconnect limits on gigascale integration (GSI) in the 21st century,” Proceedings of the IEEE, vol. 89, no. 3, pp. 305-324, 2001.
71. [12] R. Ho, K. W. Mai, and M. A. Horowitz, “The future of wires,” Proceedings of the IEEE, vol. 89, no. 4, pp. 490-504, 2001.
72. [15] M. Ieong, K. W. Guarini, V. Chan, K. Bernstein, R. Joshi, J. Kedzierski, and W. Haensch, "Three dimensional CMOS devices and integrated circuits." pp. 207-213.
73. [19] S. Matsuo, T. Nakahara, K. Tateno, H. Tsuda, and T. Kurokawa, “Hybrid integration of smart pixel with vertical-cavity surface-emitting laser using polyimide bonding,” Trends Optics Photonics, vol. 14, pp. 39-46, 1997.
74. [20] J. Forthun, and C. Belady, "3-D memory for improved system performance." pp. 667-677.
75. [21] R. E. Terrill, "Aladdin: Packaging lessons learned." p. 7.
76. [30] D. La Tulipe, L. Shi, A. Topol, S. Steen, D. Pfeiffer, D. Posillico, D. Neumayer, D. Goma, V. Vichiconti, and J. Rubino, "Critical aspects of layer transfer and alignment tolerances for 3D integration processes."
77. [31] K. Guarini, A. Topol, D. Singh, D. La Tulipe, L. Shi, A. Young, A. Alam, D. Frank, D. Neumayer, and J. Vichiconti, "Process technologies for three dimensional integration." pp. 212-214.
78. [35] J. McMahon, F. Niklaus, R. Kumar, J. Yu, J. Lu, and R. Gutmann, "CMP Compatibility of partially cured benzocyclobutene (BCB) for a via-first 3D IC process." p. W4. 4.
79. [39] J. Lu, “Wafer-level 3D hyper-integration technology platform,” Presentation, spring, 2005.
80. [40] F. Niklaus, J. Lu, J. McMahon, J. Yu, S. Lee, T. Cale, and R. Gutmann, “Wafer-level 3D integration technology platforms for ICs and MEMS,” Proc. 22nd Int. VMIC, pp. 486-493, 2005.
81. [42] P. Ramm, "EUROPEAN ACTIVITIES IN 3D SYSTEM INTEGRATION–THE e―CUBES PROJECT."
82. [43] G. Philip, B. Christopher, and P. Ramm, "Handbook of 3D integration: technology and applications of 3D integrated circuits," Wiley-VCH New York, 2008.
83. [46] R. Yu, F. Liu, R. Polastre, K. N. Chen, X. Liu, L. Shi, E. Perfecto, N. Klymko, M. Chace, and T. Shaw, "Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding." pp. 170-171.
84. [51] R. Agarwal, W. Zhang, P. Limaye, R. Labie, B. Dimcic, A. Phommahaxay, and P. Soussan, "Cu/Sn microbumps interconnect for 3D TSV chip stacking." pp. 858-863.
85. [55] C.-T. Ko, K.-N. Chen, W.-C. Lo, C.-A. Cheng, W.-C. Huang, Z.-C. Hsiao, H.-C. Fu, and Y.-H. Chen, "Wafer-level 3D integration using hybrid bonding." pp. 1-4.
86. [58] S. J. Koester, A. M. Young, R. Yu, S. Purushothaman, K.-N. Chen, D. C. La Tulipe Jr, N. Rana, L. Shi, M. R. Wordeman, and E. J. Sprogis, “Wafer-level 3D integration technology,” IBM Journal of Research and Development, vol. 52, no. 6, pp. 583-597, 2008.
87. [59] G. Van der Plas, P. Limaye, I. Loi, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, and G. Katti, “Design issues and considerations for low-cost 3-D TSV IC technology,” Solid-State Circuits, IEEE Journal of, vol. 46, no. 1, pp. 293-307, 2011.
88. [65] C. S. Tan, R. J. Gutmann, and L. R. Reif, Wafer level 3-D ICs process technology: Springer Science & Business Media, 2009.
89. [67] J.-Q. Lu, K. Rose, and S. Vitkavage, “3D Integration: Why, what, who, when?,” Future Fab Int, vol. 23, no. 23, pp. 25-26, 2007.
90. [68] M.-F. Chang, W.-C. Wu, C.-S. Lin, P.-F. Chiu, M.-B. Chen, Y.-H. Chen, H.-C. Lai, Z.-H. Lin, S.-S. Sheu, and T.-K. Ku, "A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms." pp. 74-75.
91. [70] U. Kang, H.-J. Chung, S. Heo, D.-H. Park, H. Lee, J. H. Kim, S.-H. Ahn, S.-H. Cha, J. Ahn, and D. Kwon, “8 Gb 3-D DDR3 DRAM using through-silicon-via technology,” Solid-State Circuits, IEEE Journal of, vol. 45, no. 1, pp. 111-119, 2010.
92. [71] S. K. Lim, "3D-MAPS: 3D massively parallel processor with stacked memory," Design for High Performance, Low Power, and Reliable 3D Integrated Circuits, pp. 537-560: Springer, 2013.
93. [74] W. J. Dally, and B. P. Towles, Principles and practices of interconnection networks: Elsevier, 2004.
94. [75] S. M. Sze, and K. K. Ng, Physics of semiconductor devices: John wiley & sons, 2006.
95. [77] J. Kim, J. S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, and K. Park, “High-frequency scalable electrical model and analysis of a through silicon via (TSV),” Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 1, no. 2, pp. 181-195, 2011.
96. [91] Z. Huang, R. Chatterjee, P. Justison, R. Hernandez, S. Pozder, A. Jain, E. Acosta, D. A. Gajewski, V. Mathew, and R. E. Jones, "Electromigration of Cu-Sn-Cu micropads in 3D interconnect." pp. 12-17.