單分子層摻雜與微波退火形成超淺摻雜之研究

A Study on Ultra-Shallow Doping by Molecular Monolayer Doping Technology and Microwave Annealing

卓大鈞

微波退火 ； 單層摻雜 ； 超淺摻雜 ； microwave annealing ； monolayer doping ； ultra-shallow doping

交通大學電子物理系所學位論文

2016年

博士

趙天生;李耀仁

英文

現今的互補式金氧半場效電晶體技術發展，對於短通道效應的控制將使得元件製程更趨複雜，為了解決嚴重漏電流與次臨界擺幅劣化等問題，源極/汲極區域的接面製作將會是一大重要課題，尤其是接面深度與接面電阻率。因為高溫退火會造成嚴重的摻雜物擴散，為了活化摻雜物並完成超淺、超陡峭摻雜濃度，低溫微波退火將會是一個理想的技術。 首先，我們將磷、砷、二氟化硼分別摻雜於矽基板，並使用微波退火或快速升溫退火完成摻雜物活化。在相同片電阻的情況下，微波退火的溫度將可比傳統快速升溫退火少80到140度，因此微波退火更有利於製作低阻值且未擴散的超淺接面。除了比較不同溫度下，兩種退火技術在片電阻的趨勢之外，在此也同時探討基板的溫度，因為基板溫度與微波能量的耦合，摻雜物即可在低溫的情況下完成活化。 另一方面，元件製作在三維結構上將遭遇技術上的困難，傳統的離子佈值受限於不均勻的縱向分佈，使得摻雜技術將會遭遇到挑戰。本論文中，我們發展出一種在矽材料表面進行化學分子反應的方式，利用其自我組裝的特性來達到均勻性佳、淺摻雜、無損傷的摻雜過程。由於自我侷限的反應特性將對摻雜原子分佈有更好的控制能力，因此本摻雜方式將能應用到下個世代。我們將介紹分子摻雜所形成的淺摻雜區對三閘極電晶體的影響及製程的簡化方式，並藉由微波退火機制形成淺摻雜區提升元件電特性。此外探討不同退火機制及退火次數對於源極/汲極區摻雜分佈及閘極氧化層造成的影響。 隨著元件尺寸的微縮，對於傳統金氧半場效電晶體來說，短通道效應與隨機摻雜不穩定性將是嚴重的問題。因為擁有簡單製程與較大等效閘極長度的優勢，無接面電晶體將會是一個合適的替代選擇，然而傳統離子佈植會有同一晶片摻雜不穩定的困難，對於同一晶片上的無接面電晶體來說將使得每一個電晶體的驅動電流不穩定，這也造成量子效應及較大的串聯電阻而劣化元件特性。此外為了有效地控制元件，摻雜通道區的體積必須要夠小才能達到良好的閘極控制，這將對驅動電流產生瓶頸，也限制無接面電晶體的發展可行性。為了解決上述問題，我們發展出一種新穎的無接面電晶體，利用單分子層摻雜技術完成球殼摻雜並可不受限於通道體積，由於摻雜僅在表面，閘極會有較佳的控制力(電流開關比>106)，因為該技術可減少隨機摻雜不穩定性，同時也將抑制元件臨界電壓不穩定性、次臨界擺幅劣化的問題。 最後，我們利用新穎二氧化碳雷射來提升摻雜物的活化，且該雷射具有未熔融且選擇性區域退火的優勢，相較於僅以單分子層摻雜技術與微波退火製作的球殼摻雜無接面電晶體，利用單分子層摻雜技術結合微波退火與二氧化碳雷射，球殼摻雜無接面電晶體則有更好的元件特性(電流開關比>107)及驅動電流的改善(提升160%以上)。在此也同時探討摻雜物活化的機制，先利用微波退火將摻雜物擴散至矽基板表面，接著利用二氧化碳雷射活化位於間隙位置的摻雜物。此方法應用於塊狀基板式鰭型電晶體亦有良好的元件特性，因此對於三維堆疊元件積體電路的發展將擁有極大的潛力。

For the state-of-the-art CMOSFETs technology, the fabrication process for short channel effect control will be much more complicated. To solve the problems of severe leakage and subthreshold slope degradation, formation of junctions in the source/drain regions will be an important issue for reducing the dimension of transistors, especially for junction depth and resistivity. Because high temperature annealing results in serious dopant diffusion, microwave annealing (MWA) will be an ideal technique to activate dopants and achieve ultra-shallow and abrupt doping profiles at low temperature. First, phosphorus, arsenic and BF2 implants in Si were annealed by MWA or rapid thermal annealing (RTA). Compared with the conventional RTA process, the temperature of dopant activation by MWA could be 80 to 140 °C reduction at the same sheet resistance. Therefore, MWA has the great advantage of forming ultra-shallow junction with low resistivity and without diffusion. Besides showing the trend of sheet resistance versus temperature by MWA and RTA, the substrate temperature is also discussed. Due to the combination of substrate temperature and coupling of microwave energy, the dopants could be activated at low temperature. On the other hand, device fabrication process will have some doping problems in three-dimensional structure. Due to the limitation of non-uniform vertical doping profile in conventional implantation, doping technology causes a challenge in fabrication. In this dissertation, a new doping method utilizing a chemical molecular reaction on silicon surface is developed to reach conformal, ultra-shallow, and damage-free properties. Furthermore, the self-limit quality of molecular reaction can have a better controllability on dopant distribution, which is more suitable in next technology node. We introduce the influence of the ultra-shallow regions formed by molecular doping for tri-gate transistors and the simplification process of device fabrication. Moreover, microwave annealing will be utilized to form shallow doping regions to enhance the electrical characteristics of devices. In addition, we discuss about the influence of different annealing techniques and the thermal process times on the dopant distribution of source/drain regions and the gate dielectric. With device dimension scaling, short channel effect and random dopant fluctuation are serious problems for conventional MOSFETs. A junctionless (JL) transistor is a suitable advanced FinFET candidate owing to simple processing and longer effective gate length. However, variability of JLFET performance due to random dopant fluctuation by ion implantation is projected to be a serious problem as the dopant atoms become increasingly random. It may also degrade the device performance due to quantum confinement and large series resistance. Additionally, to effectively modulate the doped region, the volume of the body must be small enough for a better gate control, bottlenecking the on-current and limiting the feasibility of JLFET. In order to solve the problems, we propose a novel JLFinFET structure with a size-quantum confinement-free fin width and a shell doping profile (SDP) formed by molecular monolayer doping (MLD). Due to the proximity of dopanted region to the gate, the device with a shallower doping depth exhibits better gate control (ION/IOFF > 106). And the reduction of VTH variation and subthreshold swing degradation is also resulted from the suppression of random dopant fluctuation. Finally, a novel CO2 laser spike annealing (COLSA) with nonmelting and selective-heating feature is used to enhance dopant activation. Formed by MLD method and MWA+COLSA, a poly-Si JLFinTFT with a novel SDP shows excellent performance (ION/IOFF >107) and on-current enhancement (>160%). The mechanism of dopant activation is investigated here, which MWA drives in and partially activates the dopants and COLSA heats the others occupied in the interstitial sites. The method is also applied in bulk FinFET structure, showing the same results with poly-Si JLFinTFTs. Our results reveal the potential for 3D stacked ICs applications.

1. Chapter 1
   連結：
2. [1.1] Yan Lai, Nicolas Cordero and James C Greer, “Modelling of Sb Activation in Ultrashallow Junction Regions in Bulk and Strained Si,” MRS Proceedings, 1070, 1070-E03-05, 2008.
   連結：
3. [1.2] J. C. Ho, R. Yerushalmi, G. Smith, P. Majhi, J. Bennett, J. Halim, V. N. Faifer, and A. Javey, “Wafer-Scale, Sub-5 nm Junction Formation by Monolayer Doping and Conventional Spike Annealing,” Nano Letters, vol. 9, pp. 725-730, 2009.
   連結：
4. [1.3] D. J. Eaglesham, P. A. Stolk, H.-J. Gossmann, and J. M. Poate, “Implantation and transient B diffusion in Si: The source of the interstitials,” Appl. Phys. Lett. 65, 2305, 1994.
   連結：
5. [1.4] N. E. B. Cowern, G. F. A. van de Walle, P. C. Zalm, and D. W. E. Vandenhoudt, “Mechanisms of implant damage annealing and transient enhanced diffusion in Si,” Appl. Phys. Lett. 65, 2981, 1994.
   連結：
6. [1.5] P. A. Stolk, H. J. Gossmann, D. J. Eaglesham, J. M. Poate, “Implantation and transient boron diffusion: the role of Si selfinterstitials,” Nucl. Instrum. Methods Phys. Res., Sect. B, 96, 187, 1995.
   連結：
7. [1.6] Anil U. Mane, Jeffrey W. Elam, Alexander Goldberg, Thomas E. Seidel, Mathew D. Halls, Michael I. Current, Joseph Despres, Oleg Byl, Ying Tang and Joseph Sweeney, “Atomic layer deposition of boron-containing films using B2F4,” J. Vac. Sci. Technol. A 34(1), 01A132-1, 2016.
   連結：
8. [1.7] W. Hei and H. Iwai, “On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology,” Microelectron. Eng. 138, 57, 2015.
   連結：
9. [1.9] G. Fuse, M. Sugitani, H. Matsushita, H. Murooka, M. Kuriyama and M. Tanaka, “Momentum transfer implantation for sidewall doping of finFETs,” SSDM 2010, paper P-1-23-L.
   連結：
10. [1.10] Y. Sasaki et al., “Improved sidewall doping of extensions by AsH3 ion assisted deposition and doping (IADD) with small implant angle for scaled NMOS Si bulk finFETs,” IEDM Tech. Dig., pp. 20.6.1 - 20.6.4, 2013.
    連結：
11. [1.11] F. Sarubbi et al., “Chemical vapor deposition of α-Boron layers on silicon for controlled nanometer-deep p+n junction formation,” J. Elec Mat, vol. 39, no. 2, 2010.
    連結：
12. [1.13] MacCrimmon, R.; Hautala, J.; Gwinn, M.; Sherman, S. “Gas cluster ion beam infusion processing of semiconductors,” Nucl. Instrum. Methods Phys. Res., Sect. B 2006, 242, 427–30.
    連結：
13. [1.14] Yon, G. H.; Buh, G. H.; Park, T.; Hong, S. J.; Shin, Y. G.; Chung, U.; Moon, J. T. “Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65 nm Technology Nodes,” Jpn. J. Appl. Phys. 2006, 45, 2961–2964.
    連結：
14. [1.15] T. L. Alford, D. C. Thompson, J. W. Mayer, N. D. Theodore, “Dopant activation in ion implanted silicon by MWA,”J. Appl. Phys., vol. 106, p. 114902, 2009.
    連結：
15. [1.16] H. Zohm, E. Kasper, P. Mehringer, G. A. Muller, “Thermal processing of silicon wafers with microwave co-heating,”Microelectron. Eng., vol. 54, pp. 247-253, 2000.
    連結：
16. [1.18] Y.-J. Lee, F.-K. Hsueh, S.-C. Huang, J. M. Kowalski, J. E. Kowalski, A. T. Y. Cheng, A. Koo, G.-L. Luo, and C.-Y. Wu, “A low-temperature microwave anneal process for boron-doped ultrathin Ge epilayer on Si substrate,” IEEE Electron Device Lett., vol. 30, no. 2, pp. 123–125, Feb. 2009.
    連結：
17. [1.19] Y.-L. Lu, F.-K. Hsueh, K.-C. Huang, T.-Y. Cheng, J. M. Kowalski, J. E. Kowalski, Y.-J. Lee, T.-S. Chao, and C.-Y. Wu, ”Nanoscale p-MOS Thin-Film Transistor With TiN Gate Electrode Fabricated by Low-Temperature Microwave Dopant Activation,” IEEE Electron Device Lett., vol. 31, no. 5, pp. 417–439, May. 2010.
    連結：
18. [1.20] F.-K. Hsueh, Y.-J. Lee, K.-L. Lin, M. I. Current, C.-Y. Wu, and T.-S. Chao, “Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave Annealing,” IEEE Trans. Electron Devices, vol. 58, pp. 2088-2093, 2011.
    連結：
19. [1.21] Y.-J. Lee, S.-S. Chuang, F.-K. Hsueh, H.-M. Lin, S.-C.Wu, C.-Y.Wu, and T.-Y. Tseng, “Dopant activation in single crystalline germanium by low temperature microwave annealing,” IEEE Electron Device Lett., vol. 32, no. 2, pp. 194–196, Feb. 2011.
    連結：
20. [1.22] J. H. Booske, R. F. Cooper, I. Dobson, “Mechanisms for nonthermal effects on ionic mobility during microwave processing of crystalline solids,” J. Mater. Res., vol. 7, pp. 495-501, 1992.
    連結：
21. [1.23] A. G. Whittaker, “Diffusion in Microwave-Heated Ceramics,” Chem. Mater., vol. 17, no. 13, pp. 3426 -3432, 2005.
    連結：
22. [1.24] K. Thompson, Yogesh B. Gianchandani, John Booske, IEEE, and Reid F. Cooper, “Direct Si-Si Bonding by Electromagnetic Induction Heating,” J. MicroElectroMechanical Systems, vol. 11, no. 4, pp. 285-292, 2002.
    連結：
23. [1.25] K. Thompson, J. H. Booske, Y. B. Gianchandani, and R. F. Cooper, “Electromagnetic Annealing for the 100 nm Technology Node,” IEEE Electron Device Lett., vol. 23, no. 3, pp. 127 – 129, 2002.
    連結：
24. [1.26] K. Thompson, John H. Booske, Reid F. Cooper, and Yogesh B. Gianchandani, “Electromagnetic Fast-Firing for Ultra-Shallow Junction Formation,” IEEE Trans Semiconductor Manufacturing, vol. 16, no. 3, pp. 460-468, 2003.
    連結：
25. [1.27] D. Stuerga, P. Gaillard, “Microwave Athermal Effects in Chemistry: A Myth's Autopsy.Part II: Orienting effects and thermodynamic consequences of electric field,” J. Microwave Power Electromangn. Energy, vol. 31, pp. 101-113, 1996.
    連結：
26. [1.28] C. O. Kappe, “Controlled Microwave Heating in Modern Organic Synthesis,” Angew. Chem. Int. Ed., vol. 43, pp. 6250-6285, 2004.
    連結：
27. [1.29] A. De la Hoz, A. Diaz-Ortiz, A. Moreno, “Microwaves In Organic Synthesis. Thermal and Non Thermal Microwave Effects,” Chem. Soc. Rev., pp. 164-178, 2005.
    連結：
28. [1.30] J. H. Booske, R. F. Cooper, S. A. Freeman, “Microwave enhanced reaction kinetics in ceramics,” Mater. Res. Innovations, vol. 1, pp. 77-84, 1997.
    連結：
29. [1.31] G. Robb, A. Harrison, A. G. Whittaker, “Temperature-resolved, in-situ powder X-ray diffraction of silver iodide under microwave irradiation,” Phys. Chem. Comm., pp. 135-137, 2002.
    連結：
30. [1.32] S. A. Freeman, J. H. Booske, R. F. Cooper, “Modeling and numerical simulations of microwave-induced ionic transport,” J. Appl. Phys., vol. 83, p. 5761, 1998.
    連結：
31. [1.34] J. H. Booske, R.F. Cooper, S.A. Freeman, K. Rybakov, and V. Semenov, “Microwave Ponderomotive Forces in Solid State Ionic Plasmas,” invited paper, Phys Plasmas, vol. 5, pp. 1664-1670, 1998.
    連結：
32. [1.35] K. Thompson, J. H. Booske, R.L. Ives, J. Lohr, Y. Gorelov, K. Kajiwara, “Millisecond Microwave Annealing: Driving Micro-Electronics Nano,” Journal of Vacuum Science and Technology B, vol. 23, pp. 970-978, 2005.
    連結：
33. [1.37] K. B. Blodgett, “Monomolecular Films of Fatty Acids on Glass,” J. Am. Chem. Soc., 56, 495-495, 1934.
    連結：
34. [1.39] G. G. Roberts, Adv. Phys., vol. 34, 475-512, 1985.
    連結：
35. [1.41] K. B. Blodgett, J. Am. Chem. Soc., 57, 1007-1022, 1935.
    連結：
36. [1.42] A. Ulman, “An introduction to Ultrathin Organic Films: From Langmuir-Blodgett to Self-Assembly,” Academic Press: Boston, 1991.
    連結：
37. [1.43] D. R. Talham, Chem. Rev., 104, 5479-5501, 2004.
    連結：
38. [1.46] J. Sagiv, J. Am. Chem. Soc., 102, 92-98, 1980.
    連結：
39. [1.47] A. Ulman, Chem. Rev., 96, 1533-1554, 1996.
    連結：
40. [1.49] P. S. Peercy, “The drive to miniaturization,” Nature 406, 1023–1026, 2000.
    連結：
41. [1.50] C. Claeys, “Technological challenges of advanced CMOS processing and their impact on design aspects,” VLSI Design, 275–282, 2004.
    連結：
42. [1.51] S. Xiong and J. Bokor, “A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices,” IEEE Trans. Electron Devices 51, 228–232, 2004.
    連結：
43. [1.52] E. C. Jones and E. Ishida, “Shallow junction doping technologies for ULSI,” Mater. Sci. Eng. 24, 1–80, 1998.
    連結：
44. [1.53] Y. H. Song, K. Y. Kim, J.C. Bae, K. Kato, E. Arakawa, K. S. Kim, K. T. Park, H. Kurino and M. Koyanagi, “A novel atomic layer doping technology for ultra-shallow junction in sub-0.1 pm MOSFETs,” IEDM Tech. Dig., pp. 505–508, 1999.
    連結：
45. [1.54] B. Kalkofen, M. Lisker and E. P. Burte, “Phosphorus diffusion into silicon after vapor phase surface adsorption of phosphine,” Mater. Sci. Eng. B 124–125, 288–292, 2005.
    連結：
46. [1.55] C. R. Moon et al., “Application of plasma-doping technique to reduce dark current of CMOS image sensors,” IEEE Electron. Dev. Lett. 28, 114–116, 2007.
    連結：
47. [1.56] Thomas E. Seidel, Alexander Goldberg, Mat D. Halls, and Michael I. Current, “Simulation of nucleation and growth of atomic layer deposition phosphorus for doping of advanced FinFETs,” J. Vac. Sci. Technol. A 34, 01A150, 2016.
    連結：
48. [1.59] J. C. Ho, R. Yerushalmi, Z. A. Jacobson, Z. Fan, R. L. Alley, and A. Javey, “Controlled nanoscale doping of semiconductors via molecular monolayers,” Nat. Materials, vol. 7, pp. 62-67, 2008.
    連結：
49. [1.61] C. J. Sandroff, R. N. Nottenburg, J. C. Bichoff, and R. Bhat, “Dramatic enhancement in the gain of a GaAs/AlGaAs heterostructure bipolar transistor by surface chemical passivation,”Appl. Phys. Lett. 51, 33, 1987.
    連結：
50. [1.62] D. Y. Petrovykh, J. M. Sullivan, and L. J. Whitman, “Quantification of discrete oxide and sulfur layers on sulfur-passivated InAs by XPS,” Surf. Interface Anal. 37, 989, 2005.
    連結：
51. [1.63] M. A. Filler and S. F. Bent, “The surface as molecular reagent: Organic chemistry at the semiconductor interface,” Prog. Surf. Sci. 73, 1–56, 2003.
    連結：
52. [1.64] M. R. Linford and C. E. D. Chidsey, “Alkyl monolayers covalently bonded to silicon surfaces,” J. Am. Chem. Soc. 115, 12631–12632, 1993.
    連結：
53. [1.65] L. J. Webb and N. S. Lewis, “Comparison of the electrical properties and chemical stability of crystalline silicon (111) surfaces alkylated using grignard reagents or olefins with Lewis acid catalysts,” J. Phys. Chem. B 107, 5404–5412, 2003.
    連結：
54. [1.66] Jillian M. Buriak, “Organometallic Chemistry on Silicon and Germanium Surfaces,” Chemical Reviews, Vol. 102, No. 5, 2002
    連結：
55. [1.67] C. Chatgilialoglu, “Organosilanes as radical-based reducing agents in synthesis,”Acc. Chem. Res., 25, 188, 1992.
    連結：
56. [2.1] International Technology Roadmap for Semiconductor, [Online]. Available: http://www.itrs2.net/
    連結：
57. [2.2] D. K. Schroder, Semiconductor Material and Device Characterization. Hoboken, NJ :Wiley, 2006.
    連結：
58. [2.3] Q. Zhang, J. Huang, N. Wu, G. Chen, M. Hong, L. K. Bera, and C. Zhu, “Drive-current enhancement in Ge n-channel MOSFET using laser annealing for source/drain activation,” IEEE Electron Device Lett., vol. 27, no. 9, pp. 728–730, Sep. 2006.
    連結：
59. [2.4] A. T. Fiory, H.-J. Gossmann, C. Rafferty, P. Frisella, J. Hebb, and J. Jackson, “Ultra-shallow junctions and the effect of ramp-up rate during spike anneals in lamp-based and hot-walled RTP systems,” in Proc. Int. Conf. Ion Implantation Technol., Kyoto, Japan, pp. 22–25, Jun. 22–26, 1998.
    連結：
60. [2.5] C. F. Nieh, K. C. Ku, C. H. Chen, H. Chang, L. T. Wang, L. P. Huang, Y. M. Sheu, C. C. Wang, T. L. Lee, S. C. Chen, M. S. Liang, and J. Gong, “Millisecond anneal and short-channel effect control in Si CMOS transistor performance,” IEEE Electron Device Lett., vol. 27, no. 12, pp. 969–971, Dec. 2006.
    連結：
61. [2.8] F.-K. Hsueh, Y.-J. Lee, K.-L. Lin, M. I. Current, C.-Y. Wu, and T.-S. Chao, “Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave Annealing,” IEEE Trans. Electron Devices, vol. 58, pp. 2088-2093, 2011.
    連結：
62. [2.9] Y.-J. Lee, S.-S. Chuang, F.-K. Hsueh, H.-M. Lin, S.-C.Wu, C.-Y.Wu, and T.-Y. Tseng, “Dopant activation in single crystalline germanium by low temperature microwave annealing,” IEEE Electron Device Lett., vol. 32, no. 2, pp. 194–196, Feb. 2011.
    連結：
63. [2.11] T. Sato, “Spectral Emissivity of Silicon,” Jpn. J. Appl. Phys. 6:339, 1967.
    連結：
64. [2.12] B. Sopori, W. Chen, J. Madjdpour and N. M. Ravindra, “Calculation of Emissivity of Si Wafers,” Journal of Electronic Materials, vol. 28, no. 12, 1999.
    連結：
65. [3.1] Masanobu Saito, Takashi Yoshitomi, Hisashi Hara, Mizuki Ono, Yasushi Akasaka, “P-MOSFET’s with Ultra-Shallow Solid-Phase-Diffused Drain Structure Produced by Diffusion from BSG Gate-Sidewall,” IEEE Trans. Electron Devices, vol. 40, no. 12, pp. 2264-2272, 1993.
    連結：
66. [3.2] Y. Kiyota, “Surface Reaction Doping using Gas Source for Ultra Shallow Junctions,” Junction Technology, pp. 19-22, 2000.
    連結：
67. [3.3] P. G. Carey, T. W. Sigmon, R. L. Press, and T. S. Fahlen, “Ultra-Shallow High-Concentration Boron Profiles For CMOS Processing, ”IEEE Electron Device Lett., vol. 6, no. 6, 1985.
    連結：
68. [3.4] J. Foggiato and W. S. Yoo, “Implementation of flash technology for ultra- shallow junction formation: Challenges in process integration,” J. Vac. Sci. Technol. B 24, 515, 2006.
    連結：
69. [3.8] Y. Kiyaota, M. Matsushima, Y. Kaneto, M. Kanetomo, Y. Tamaki, K. Muraki and T. Inada, “Ultrashallow p‐type layer formation by rapid vapor‐phase doping using a lamp annealing apparatus,” Appl. Phys. Lett. vol. 64, pp. 910, 1994.
    連結：
70. [3.9] Y. H. Song, K. Y. Kim, J.C. Bae, K. Kato, E. Arakawa, K. S. Kim, K. T. Park, H. Kurino and M. Koyanagi, “A Novel Atomic Layer Doping Technology for Ultra-shallow Junction in Sub-0.1 μm MOSFETs,” IEDM Tech. Dig., pp. 505, 1999
    連結：
71. [3.10] P. S. Peercy, “The drive to miniaturization,” Nature , 406, 1023–1026, 2000.
    連結：
72. [3.11] C. Claeys, “Technological challenges of advanced CMOS processing and their impact on design aspects,” VLSI Design, 275–282, 2004.
    連結：
73. [3.12] J. C. Ho, R. Yerushalmi, Z. A. Jacobson, Z. Fan, R. L. Alley and A. Javey,“ Controlled nanoscale doping of semiconductors via molecular monolayers,” Nat. Materials, vol. 7, pp. 62-67, 2008.
    連結：
74. [3.14] Y. L. Chen, C. A. Helm, and J. N. Israelachvili., “Molecular Mechanisms Associated with Adhesion and Contact Angle Hysteresis of Monolayer Surfaces,” J. Phys. Chem. 1991, 95, 10736-10747
    連結：
75. [3.15] M. Beebe, J. Bennett, J. Barnett, A. Berlin and T. Yoshinaka, “Quantifying residual and surface carbon using polyencapsulation SIMS,” Appl. Surf. Sci. 2004, 231-32, 716–19.
    連結：
76. [3.16] J. C. Ho, R. Yerushalmi, G. Smith, P. Majhi, J. Bennett, J. Halim, V. N. Faifer, and A. Javey, “Wafer-Scale, Sub-5 nm Junction Formation by Monolayer Doping and Conventional Spike Annealing,” Nano Letters, vol. 9, pp. 725-730, 2009.
    連結：
77. [3.17] J. T. C. Chen, T. Dimitrova, D. Dimitrov, “A New Method for Mapping Ultra-Shallow Junction Leakage Currents,” International Workshop on IWJT, IEEE 2006, pp. 100-103.
    連結：
78. [4.2] T.-H. Yu, Ethan Hsu, C.-W. Liu, J.-P. Colinge, Y.-M. Sheu, Jeff Wu, and C.H. Diaz, “Electrostatics and Ballistic Transport Studies in Junctionless Nanowire Transistors,” Proc. Int. Conf. SISPAD , pp.85 -88, 2013
    連結：
79. [4.4] A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, “Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs,” IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1837–1852, Sep. 2003.
    連結：
80. [4.7] Y.-J. Lee, T.-C. Cho, K.-H. Kao, P.-J. Sung, F.-K. Hsueh, P.-C. Huang, C.-T. Wu, S.-H. Hsu, W. -H. Huang, H.-C. Chen, Y. Li, M. I. Current, B. Hengstebeck, J. Marino, T. Büyüklimanli, J.-M. Shieh, T.-S. Chao, W.-F. Wu, and W.-K. Yeh, “A novel junctionless FinFET structure with sub-5 nm shell doping profile by molecular monolayer doping and microwave annealing,” IEDM Tech. Dig., 2014, pp. 32.7.1–32.7.4.
    連結：
81. [4.9] A. Bentzen, G. Schubert, J. S. Christensen, B. G. Svensson and A. Holt, “Influence of temperature during phosphorus emitter diffusion from a spray-on source in multicrystalline silicon solar cell processing,” Prog. PhotoVoltaics 2007, 15, 281–289.
    連結：
82. [4.10] M. Uematsu, “Simulation of boron, phosphorus, and arsenic diffusion in silicon based on an integrated diffusion model, and the anomalous phosphorus diffusion mechanism,” J. Appl. Phys. 1997, 82-5, 2229.
    連結：
83. [4.12] U. Gösele, W. Frank, and A. Seeger, “Mechanism and kinetics of the diffusion of gold in silicon,” Appl. Phys. 23, 361, 1980.
    連結：
84. [4.13] U. Gösele and F. Morehead, “Diffusion of zinc in gallium arsenide: A new model,” J. Appl. Phys. 52, 4617, 1981.
    連結：
85. [4.14] N. E. B. Cowern, “General model for intrinsic dopant diffusion in silicon under nonequilibrium point‐defect conditions,” J. Appl. Phys. 64, 4484, 1988.
    連結：
86. [4.15] C.-J. Su, T.-I Tsai, Y.-L. Liou, Z.-M. Lin, H.-C. Lin, and T.-S. Chao, “Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 521–523, April 2011.
    連結：
87. [4.16] H.-C. Lin, C.-I Lin, and T.-Y. Huang, “Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors With an Ultrathin Channel,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 53–55, January 2012.
    連結：
88. [4.17] H.-C. Lin, C.-I Lin, Z.-M. Lin, B.-S. Shie, and Tiao-Yuan Huang, “Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness,” IEEE Trans. Electron Devices, vol. 60, no. 3, pp. 1142-1148, 2013.
    連結：
89. [5.2] Y.-J. Lee, T.-C. Cho, K.-H. Kao, P.-J. Sung, F.-K. Hsueh, P.-C. Huang, C.-T. Wu, S.-H. Hsu, W. -H. Huang, H.-C. Chen, Y. Li, M. I. Current, B. Hengstebeck, J. Marino, T. Büyüklimanli, J.-M. Shieh, T.-S. Chao, W.-F. Wu, and W.-K. Yeh, “A novel junctionless FinFET structure with sub-5 nm shell doping profile by molecular monolayer doping and microwave annealing,” in IEDM Tech. Dig., Dec. 2014, pp. 32.7.1–32.7.4.
    連結：
90. [5.5] M. P. V. Kumar, C.-Y. Hu, K.-H. Kao, Y.-J. Lee, and T.-S. Chao, “Impact of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs,” IEEE Trans. Electron Devices, vol. 62, pp. 3541-3546, 2015.
    連結：
91. [5.6] E. Machida, Y. Uraoka, T. Fuyuki, R. Kokawa, T. Ito and H. Ikenoue, “Characterization of local electrical properties of polycrystalline silicon thin films and hydrogen termination effect by conductive atomic force microscopy,” Appl. Phys. Lett. 94, 182104, 2009.
    連結：
92. [5.7] S. Stathopoulos, A. Florakis, G. Tzortzis, T. Laspas, A. Triantafyllopoulos, Y. Spiegel, F. Torregrosa, and D. Tsoukalas, “CO2 Laser Annealing for USJ Formation in Silicon: Comparison of Simulation and Experiment,” IEEE Trans. Electron Devices, vol. 61, pp.696-701, 2014.
    連結：
93. [5.8] D. Bäuerle, Laser Processing and Chemistry. New York, NY, USA: Springer-Verlag, 2011.
    連結：
94. [5.9] J. Narayan, R. B. James, O. W. Holland, and M. J. Aziz, “Pulsed excimer and CO2 laser annealing of ion-implanted silicon,” J. Vac. Sci. Technol., vol. 3, no. 4, pp. 1836–1838, Jul. 1985.
    連結：
95. [5.14] M.-S. Yeh, Y.-C. Wu, M.-H. Wu, Y.-R. Jhan, M.-H. Chung, and M.-F. Hung, “High performance ultra-thin body (2.4nm) poly-Si junctionless thin film transistors with a trench structure,” IEDM Tech. Dig., p. 26.6.1, 2014.
    連結：
96. [5.15] H.-C. Lin, C.-I Lin, and T.-Y. Huang, “Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors With an Ultrathin Channel,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 53–55, January 2012.
    連結：
97. [5.16] H.-C. Lin, C.-I Lin, Z.-M. Lin, B.-S. Shie, and Tiao-Yuan Huang, “Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness,” IEEE Trans. Electron Devices, vol. 60, no. 3, pp. 1142-1148, 2013.
    連結：
98. [6.1] Y. Tian, R. Huang, Y. Wang, J. Zhuge, R. Wang, J. Liu, X. Zhang, and Y. Wang, “New Self-Aligned Silicon Nanowire Transistors on Bulk Substrate Fabricated by Epi-Free Compatible CMOS Technology: Process Integration, Experimental Characterization of Carrier Transport and Low Frequency noise,” IEDM Tech. Dig., pp. 895 - 898, 2007.
    連結：
99. [6.2] N. Singh, K. D. Buddharaju, S. K. Manhas, A. Agarwal, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, “Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications,” IEEE Trans. Electron Device, vol. 55, no. 11, pp. 3107-3118, 2008.
    連結：
100. [1.8] T. E. Seidel, M. D. Halls, A. Goldberg, J. W. Elam, A. Mane, and M. I. Current, “Atomic Layer Deposition of Dopants for Recoil Implantation in finFET Sidewalls,” 2014 20th International Conference on Ion Implantation Technology (IIT); p1-4, 2014
101. [1.12] Kawasaki, Y.; Kuroi, T.; Yamashita, T.; Horita, K.; Hayashi, T.; Ishibashi, M.; Togawa, M.; Ohno, Y.; Yoneda, M.; Horshy, T.; Jacobson, D.; Krull, W. “Ultra-shallow junction formation by B18H22 ion implantation,” Nucl. Instrum. Methods Phys. Res., Sect. B 2005, 237, 25–29.
102. [1.17] Y.-J. Lee, Y.-L. Lu, F.-K. Hsueh, K.-C. Huang, C.-C. Wan, T.-Y. Cheng, M.-H. Han, J. M. Kowalski, J. E. Kowalski, D. Heh, H.-T. Chuang, Y. Li, T.-S. Chao, C.-Y. Wu, and F.-L. Yang, “3D 65 nm CMOS with 320 ◦C microwave dopant activation,” in IEDM Tech. Dig., pp. 31–34., 2009
103. [1.33] J. H. Booske, University of Wisconsin-Madison, USA, private communications, 2010.
104. [1.36] Y.-J. Lee, T.-C. Cho, S.-S. Chuang, F.-K. Hsueh, Y.-L. Lu, P.-J. Sung, H.-C. Chen, M. I. Current, T.-Y. Tseng, T.-S. Chao, Chenming Hu, and F.-L. Yang, “Low-temperature microwave annealing processes for future IC fabrication—A review,” IEEE Trans. Electron Devices, vol. 61, no. 3, pp. 651–665, Mar. 2014.
105. [1.38] W. C. Bigelow, D. L. Pickett, W. A Zisman, J. Coll. Sci. Imp., 1, 513-538, 1946.
106. [1.40] Jurjen ter Maat, “Modification of inorganic surfaces with alkenes and alkynes,” 2012.
107. [1.44] J. A. Zasadzinski, R. Viswanathan, L. Madsen, J. Garnaes, D. K. Schwartz, Science, 263, 1726-1733, 1994.
108. [1.45] J. J. Gun, R. Iscovici and J. Sagiv, J. Colloid Interf. Sci., 101, 201-213, 1984.
109. [1.48] M. R. Linord, P. Fenter, P. M. Eisenberger, C. E. D. Chidsey, J. Am. Chem. Soc., 117, 3145-3155, 1995.
110. [1.57] K.-W. Ang, J. Barnett, W.-Y. Loh, J. Huang, B.-G. Min, P. Y. Hung, I. Ok, J. H. Yum, G. Bersuker, M. Rodgers, V. Kaushik, S. Gausepohl, C. Hobbs, P. D. Kirsch, and R. Jammy, IEDM Tech. Dig., pp. 837, 2011.
111. [1.58] J. H. Yum, H. S. Shin, R. Hill, J. Oh, H. D. Lee, Ryan M. Mushinski, Todd W. Hudnall, C. W. Bielawski, S. K. Banerjee, W. Y. Loh, Wei-E Wang and Paul Kirsch, “A study of capping layers for sulfur monolayer doping on III-V junctions,” Appl. Phys. Lett. 101, 253514, 2012.
112. [1.60] J. C. Ho, A. C. Ford, Y. Chueh, P. W. Leu, O. Ergen, K. Takei, G. Smith, P. Majhi, J. Bennett, and A. Javey, “Nanoscale doping of InAs via sulfur monolayers,” Appl. Phys. Lett. 95, 072108, 2009.
113. Chapter 2
114. [2.6] W. Aderhold, I. Iliopoulos, and A. Hunter, “Virtual metrology in RTP with WISR,” in Proc. 15th IEEE Int. Conf. Adv. Therm. Process. Semicond.—RTP, 2007, pp. 101–104.
115. [2.7] J. D. Plummer, M. D. Deal, and P. B. Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling. Upper Saddle River, NJ: Prentice-Hall, 2000.
116. [2.10] N. M. Ravindra, B. Sopori, O. H. Gokce, S. X. Cheng, A. Shenoy, L. Jin, S. Abedrabbo, W. Chen and Y. Zhang, “Emissivity Measurements and Modeling of Silicon-Related Materials: An Overview,” International Journal of Thermophysics, vol. 22, no. 5, September 2001.
117. [2.13] Y.-J. Lee, T.-C. Cho, S.-S. Chuang, F.-K. Hsueh, Y.-L. Lu, P.-J. Sung, H.-C. Chen, M. I. Current, T.-Y. Tseng, T.-S. Chao, Chenming Hu, and F.-L. Yang, “Low-temperature microwave annealing processes for future IC fabrication—A review,” IEEE Trans. Electron Devices, vol. 61, no. 3, pp. 651–665, Mar. 2014.
118. Chapter 3
119. [3.5] International Technology Roadmap for Semiconductor, [Online]. Available: http://www.itrs2.net/
120. [3.6] Alexei Nazarov, “Semiconductor-On-Insulator Material For Nanoelectronics Applications,” Springer, 2011.
121. [3.7] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito and H. Iwai, IEDM Tech. Dig., pp. S93, 1994.
122. [3.13] K.-W. Ang, J. Barnett, W.-Y. Loh, J. Huang, B.-G. Min, P. Y. Hung, I. Ok, J. H. Yum, G. Bersuker, M. Rodgers, V. Kaushik, S. Gausepohl, C. Hobbs, P. D. Kirsch, and R. Jammy, “300mm FinFET Results Utilizing Conformal, Damage Free, Ultra Shallow Junctions (Xj~5nm) Formed with Molecular Monolayer Doping Technique,” IEDM Tech. Dig., pp. 837-840, 2011.
123. Chapter 4
124. [4.1] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
125. [4.3] H.-B. Chen, Y.-C. Wu, C.-Y. Chang, M.-H. Han, N.-H. Lu, and Y.-C. Cheng, “Performance of GAA poly-Si nanosheet (2 nm) channel of junctionless transistors with ideal subthreshold slope,” in VLSI Tech. Dig., 2013, pp. T232–T233.
126. [4.5] K.-W. Ang, J. Barnett, W.-Y. Loh, J. Huang, B.-G. Min, P. Y. Hung, I. Ok, J. H. Yum, G. Bersuker, M. Rodgers, V. Kaushik, S. Gausepohl, C. Hobbs, P. D. Kirsch, and R. Jammy, “300mm FinFET Results Utilizing Conformal, Damage Free, Ultra Shallow Junctions (Xj~5nm) Formed with Molecular Monolayer Doping Technique,” IEDM Tech. Dig., pp. 837-840, 2011.
127. [4.6] Y.-J. Lee, T.-C. Cho, S.-S. Chuang, F.-K. Hsueh, Y.-L. Lu, T.-Y. Cheng, P.-J. Sung, H.-C. Chen, M. I. Current, T.-Y. Tseng, T.-S. Chao, Chenming Hu, and F.-L. Yang, “Low-temperature microwave annealing processes for future IC fabrication—A review,” IEEE Trans. Electron Devices, vol. 61, no. 3, pp. 651–665, Mar. 2014.
128. [4.8] Sentaurus Device, Synopsys, Version G-2012.
129. [4.11] U. Gösele, in Microelectronic Materials and Processes, edited by R. A. Levy (Kluwer Academic, Norwell, MA, 1989), p. 583.
130. Chapter 5
131. [5.1] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
132. [5.3] Y.-J. Lee, T.-C. Cho, S.-S. Chuang, F.-K. Hsueh, Y.-L. Lu, T.-Y. Cheng, P.-J. Sung, H.-C. Chen, M. I. Current, T.-Y. Tseng, T.-S. Chao, Chenming Hu, and F.-L. Yang, “Low-temperature microwave annealing processes for future IC fabrication—A review,” IEEE Trans. Electron Devices, vol. 61, no. 3, pp. 651–665, Mar. 2014.
133. [5.4] Y.-J. Lee, S.-S. Chuang, C.-I. Liu, F.-K. Hsueh ; P.-J. Sung, H.-C. Chen, C.-T. Wu, K.-L. Lin, J.-Y. Yao, Y.-L. Shen, M.-L. Kuo, C.-H. Yang, G.-L. Luo, H.-W. Chen, C.-H. Lai, M. I. Current, C.-Y. Wu, Y.-M. Wan, T.-Y. Tseng, Chenming Hu, and F. -L. Yang, “Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and Ultrathin 7.5nm Ni mono-germanide,” IEDM Tech. Dig., p. 23.3.1, 2012.
134. [5.10] Y.-J. Lee., T.-C. Cho, P.-J. Sung, K.-H. Kao, F.-K. Hsueh, F.-J. Hou, P.-C. Chen, H.-C. Chen, C.-T. Wu, S.-H. Hsu, Y.-J. Chen, Y.-M. Huang, Y.-F. Hou, W.-H. Huang, C.-C. Yang, B.-Y. Chen, K.-L. Lin, M.-C. Chen, C.-H. Shen, G.-W. Huang, K.-P. Huang, M. I. Current, Y. Li, S. Samukawa, W.-F. Wu, J.-M. Shieh, T.-S. Chao, and W.-K. Yeh, “High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications,” IEDM Tech. Dig., 2015, pp. 6.2.1–6.2.4.
135. [5.11] F. A. Khaja, H.-J. L. Gossmann, B. Colombeau, and T. Thanigaivelan, “Bulk FinFET junction isolation by heavy species and thermal implants,” Ion Implantation Technology (IIT), 2014 20th International Conference on
136. [5.12] Sriramkumar Venugopalan, Muhammed A. Karim, Ali M. Niknejad and Chenming Hu, “Compact Models for Real Device Effects in FinFETs,” SISPAD 2012.
137. [5.13] K. Okano, T. Izumida, H. Kawasaki, A. Kaneko, A. Yagishita, T. Kanemura, M. Kondo, S. Ito, N. Aoki, K. Miyano, T. Ono, K. Yahashi, K. Iwade, T. Kubota, T. Matsushita, I. Mizushima, S. Inaba, K. Ishimaru, K. Suguro, K. Eguchi, Y. Tsunashima, and H. Ishiuchi, “Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length,” IEDM Tech. Dig., pp. 721 - 724, 2005.
138. Chapter 6
139. [6.3] S. D. Suk, S.-Y. Lee, S.-M. Kim, E.-J. Yoon, M.-S. Kim, M. Li, C. W. Oh, K. H. Yeo, S. H. Kim, D.-S. Shin, K.-H. Lee, H. S. Park, J. N. Han, C. J. Park, J.-B. Park, D.-W. Kim, D. Park, and B.-Il Ryu, “High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability,” IEDM Tech. Dig., pp. 717 - 720, 2005.