考通量理器中的行之工作群映射快取管理制

HETEROGENEITY-AWARE WORK-GROUP MAPPING AND CACHE MANAGEMENT FOR MODERN GPUS

毛沙敏

SBM ； Kernels ； Resource usage ； SBM ； Kernels ； Resource usage

交通大學電機資訊國際學位學程學位論文

2016年

碩士

賴伯承

英文

1. title = {Multi2Sim: A Simulation Framework for CPU-GPU Computing},
   連結：
2. booktitle = {Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques},
   連結：
3. keywords = {CPU-GPU, heterogeneous computing, multi2sim, simulation},
   連結：
4. author={M. Lee and J. h. Jeon and J. Kim and J. Song},
   連結：
5. title={Scalable and Parallel Implementation of a Financial Application on a GPU: With Focus on Out-of-Core Case},
   連結：
6. year={2010},
   連結：
7. title={Porting a neuro-imaging application to a CPU-GPU cluster},
   連結：
8. booktitle={Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE},
   連結：
9. title={Implementing Geant4 on GPU for medical applications},
   連結：
10. year={2011},
    連結：
11. title={How far is the GPU technology from practical power system applications?},
    連結：
12. title={The GAP project - GPU for realtime applications in high energy physics and medical imaging},
    連結：
13. title={TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture},
    連結：
14. title={Runtime Support for Adaptive Spatial Partitioning and Inter-Kernel Communication on GPUs},
    連結：
15. title = {Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications},
    連結：
16. location = {Salt Lake City, UT, USA},
    連結：
17. publisher = {ACM},
    連結：
18. keywords = {CUDA Streams, GPGPUs, Memory System},
    連結：
19. booktitle={Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques},
    連結：
20. title={Coordinated static and dynamic cache bypassing for GPUs},
    連結：
21. title={Adaptive Cache Bypassing for Inclusive Last Level Caches},
    連結：
22. year={2013},
    連結：
23. title={Run-time cache bypassing},
    連結：
24. author={M. Kharbutli and Y. Solihin},
    連結：
25. journal={IEEE Transactions on Computers},
    連結：
26. title={Counter-Based Cache Replacement and Bypassing Algorithms},
    連結：
27. booktitle={Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on},
    連結：
28. title={Power consumption awareness in cache memory design with SystemC},
    連結：
29. year={2004},
    連結：
30. author = {Mark Harris},
    連結：
31. title = {{ASYNCHRONOUS SHADERS: UNLOCKING THE FULL POTENTIAL OF THE GPU}},
    連結：
32. year = {2015},
    連結：
33. author = {Thomas Bradley},
    連結：
34. title = {{AMD GRAPHICS CORES NEXT (GCN) ARCHITECTURE}},
    連結：
35. year = {2012},
    連結：
36. year = {2014},
    連結：
37. title={An improved GPU MapReduce framework for data intensive applications},
    連結：
38. title={Coordinating the use of GPU and CPU for improving performance of compute intensive applications},
    連結：
39. @inproceedings{multi2sim,
40. author = {Ubal, Rafael and Jang, Byunghyun and Mistry, Perhaad and Schaa, Dana and Kaeli, David},
41. series = {PACT '12},
42. isbn = {978-1-4503-1182-3},
43. location = {Minneapolis, Minnesota, USA},
44. pages = {335--344},
45. numpages = {10},
46. url = {http://doi.acm.org/10.1145/2370816.2370865},
47. doi = {10.1145/2370816.2370865},
48. acmid = {2370865},
49. @INPROCEEDINGS{financial_app,
50. booktitle={Computer and Information Technology (CIT), 2010 IEEE 10th International Conference on},
51. pages={1323-1327},
52. keywords={computer graphic equipment;coprocessors;financial data processing;parallel programming;GPU;financial application;general purpose GPU computing;graphic processing unit;out-of-core case;parallel implementation;parallel programming;scalable implementation;Arrays;Computational modeling;Graphics processing unit;Instruction sets;Kernel;Monte Carlo methods;Random variables;GPU;High Performance Computing;Monte-Carlo simulation;Shared-Memor;out-of-core},
53. doi={10.1109/CIT.2010.238},
54. month={June},}
55. @INPROCEEDINGS{neuro_imaging_app,
56. author={R. S. Nakhjavani and S. Sharify and A. B. Hashemi and A. W. Lu and C. Amza and S. Strother},
57. booktitle={High Performance Computing Simulation (HPCS), 2014 International Conference on},
58. pages={137-145},
59. keywords={graphics processing units;medical image processing;neurophysiology;parallel processing;scheduling;CPU-GPU cluster;HPC clusters;MCT;NPAIRS;Sufferage scheduling algorithms;Torque;graphical processing units;heterogeneous cluster;linear algebra operations;neuroimaging application;nonexpert biomedical scientists;Eigenvalues and eigenfunctions;Graphics processing units;Java;Job shop scheduling;Libraries;Principal component analysis;Scheduling algorithms},
60. doi={10.1109/HPCSim.2014.6903679},
61. @INPROCEEDINGS{medical_imaging_app,
62. author={H. Perez-Ponce and Z. El Bitar and Y. Boursier and D. Vintache and A. Bonissent and C. Morel and D. Brasse and D. Visvikis and J. Bert},
63. pages={2703-2707},
64. keywords={Monte Carlo methods;emission tomography;graphics processing units;medical computing;radiation therapy;GPU;Geant4 implementation;Monte Carlo simulation;computer clusters;dosimetry;emission tomography;graphics processing units;medical applications;medical imaging;photon physics;radiotherapy;Computational modeling;Graphics processing unit;Monte Carlo methods;Navigation;Photonics;Scattering},
65. doi={10.1109/NSSMIC.2011.6152953},
66. @INPROCEEDINGS{power_system_app,
67. author={Z. Li and J. Zhu and F. Yang},
68. booktitle={2014 IEEE PES General Meeting
69. pages={1-5},
70. keywords={graphics processing units;power system simulation;smart power grids;GPU technology;graphic processing unit;large scale power system;power system applications;smart grid technologies;Computational modeling;Graphics processing units;Load modeling;Optimization;Power grids;Runtime;Transportation;Graphic Process Unit (GPU);Smart Grid;affordable high performance computation platform;power system simulation and analysis},
71. doi={10.1109/PESGM.2014.6939132},
72. ISSN={1932-5517},
73. month={July},}
74. @INPROCEEDINGS{high_energy_physics,
75. author={R. Ammendola and M. Bauce and A. Biagioni and R. Fantechi and M. Fiorini and S. Giagu and E. Graverini and G. Lamanna and A. Lonardo and A. Messina and F. Pantaleo and R. Piandani and M. Rescigno and F. Simula and M. Sozzi and P. Vicini},
76. booktitle={2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC)},
77. pages={1-7},
78. keywords={biomedical imaging;data acquisition;graphics processing units;high energy physics instrumentation computing;position sensitive particle detectors;software selection;ATLAS experiment;CERN;DAQ systems;GAP project;GPU applications;GPU latency steady reduction;GPU pilot project;NA62 experiment field test;commercial GPU parallel computing power;commercial multicore PC farms;general-purpose commodity systems;general-purpose computing;graphics processing units;hardware implementation;high energy physics data acquisition;high energy physics experiments;high level triggers;medical imaging;memory throughput;muon trigger;offline computation accelration;online parallel computing;online triggering applications;particle physics experiments;pure software selection system;realtime applications;realtime high energy physics applications;synchronous low level fixed-latency triggers;trigger development;trigger level reduction;trigger systems;very innovative approach;Data transfer;Graphics processing units;Hardware;Kernel;Protocols;Real-time systems;Standards},
79. doi={10.1109/NSSMIC.2013.6829757},
80. ISSN={1082-3654},
81. @INPROCEEDINGS{tap_tlp,
82. author={J. Lee and H. Kim},
83. booktitle={IEEE International Symposium on High-Performance Comp Architecture},
84. pages={1-12},
85. keywords={cache storage;graphics processing units;CPU-GPU heterogeneous architecture;TAP;TAP-RRIP;TAP-UCP;TLP-aware cache management policy;core-sampling mechanism;dynamic cache partitioning;last-level cache management;promotion-based cache management;rereference interval prediction;several shared cache management mechanisms;shared resource management;thread-level parallelism;utility-based cache partitioning;Benchmark testing;Computer architecture;Graphics processing unit;Instruction sets;Measurement;Radiation detectors;System-on-a-chip},
86. doi={10.1109/HPCA.2012.6168947},
87. @INPROCEEDINGS{adaptiveSpatialPartitioning,
88. author={Y. Ukidave and C. Kalra and D. Kaeli and P. Mistry and D. Schaa},
89. booktitle={Computer Architecture and High Performance Computing (SBAC-PAD), 2014 IEEE 26th International Symposium on},
90. pages={168-175},
91. keywords={graphics processing units;operating system kernels;scheduling;GPU;OpenCL runtime environment;adaptive spatial partitioning;dynamic spatial partitioning;interkernel communication;runtime support;scheduling mechanism;Benchmark testing;Graphics processing units;Kernel;Performance evaluation;Processor scheduling;Resource management;Runtime},
92. doi={10.1109/SBAC-PAD.2014.43},
93. ISSN={1550-6533},
94. month={Oct},}
95. @inproceedings{applicationAwareMemory,
96. author = {Jog, Adwait and Bolotin, Evgeny and Guz, Zvika and Parker, Mike and Keckler, Stephen W. and Kandemir, Mahmut T. and Das, Chita R.},
97. booktitle = {Proceedings of Workshop on General Purpose Processing Using GPUs},
98. series = {GPGPU-7},
99. isbn = {978-1-4503-2766-4},
100. pages = {1:1--1:8},
101. articleno = {1},
102. numpages = {8},
103. url = {http://doi.acm.org/10.1145/2576779.2576780},
104. doi = {10.1145/2576779.2576780},
105. acmid = {2576780},
106. address = {New York, NY, USA},
107. @INPROCEEDINGS{managing_shared_cache,
108. author={V. Mekkat and A. Holey and P. C. Yew and A. Zhai},
109. title={Managing shared last-level cache in a heterogeneous multicore processor},
110. pages={225-234},
111. keywords={cache storage;graphics processing units;multi-threading;multiprocessing systems;resource allocation;CPU cores;GPU LLC access throttling;GPU application;GPU cores;GPU threads;GPU tolerance;HeLM;LLC misses;LRU policy;TAP-RRIP;cache management policies;cache sensitive CPU applications;data-parallel accelerators;heterogeneous LLC management;heterogeneous multicore processors;latency tolerance;memory access latency;on-chip resources sharing;shared LLC management policy;shared last-level cache management;thread-level parallelism;Benchmark testing;Graphics processing units;Instruction sets;Multicore processing;Runtime;Sensitivity;cache management policy;heterogeneous multicores;shared last-level cache},
112. doi={10.1109/PACT.2013.6618819},
113. ISSN={1089-795X},
114. @INPROCEEDINGS{coordinated_sd_cache_bypassing,
115. author={X. Xie and Y. Liang and Y. Wang and G. Sun and T. Wang},
116. booktitle={2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)},
117. pages={76-88},
118. keywords={cache storage;graphics processing units;multi-threading;parallel architectures;CUDA programming model;GPUs;bypass preferences;cache resource contention problem;compile-time analysis;coordinated dynamic cache bypassing;coordinated static cache bypassing;dynamic bypassing technique;graphics processing units;memory divergence problems;on-chip memory;parallel architecture;run-time management;scratchpad memory;thread blocks;thread contention;Arrays;Graphics processing units;Instruction sets;Kernel;Pipelines;Synchronization;System-on-chip},
119. doi={10.1109/HPCA.2015.7056023},
120. ISSN={1530-0897},
121. month={Feb},}
122. @INPROCEEDINGS{bypassing_buffer,
123. author={S. Gupta and H. Gao and H. Zhou},
124. booktitle={Parallel Distributed Processing (IPDPS), 2013 IEEE 27th International Symposium on},
125. pages={1243-1253},
126. keywords={cache storage;cost reduction;memory architecture;performance evaluation;LLC performance enhancement;adaptive cache bypassing;bypass buffer;cache bypassing algorithm;cache hierarchy design;cache lines;cache replacement;hardware implementation cost reduction;high performance caches;inclusive last level caches;last level cache performance enhancement;upper level caches;usage information;Algorithm design and analysis;Art;Benchmark testing;Buffer storage;Coherence;Hardware;Resource management;Last level cache;cache bypassing;cache replacement policy;inclusion property},
127. doi={10.1109/IPDPS.2013.16},
128. ISSN={1530-2075},
129. month={May},}
130. @ARTICLE{cpu_bypassing_one,
131. author={T. L. Johnson and D. A. Connors and M. C. Merten and W. M. W. Hwu},
132. year={1999},
133. volume={48},
134. number={12},
135. pages={1338-1354},
136. keywords={cache storage;intelligent control;storage management;cache management;compiler techniques;instruction caches;integer programs;intelligent control;memory performance;microarchitecture scheme;run-time cache bypassing;trace-driven simulations;upper bounds;Delay;Hardware;Intelligent control;Memory management;Microarchitecture;Optimizing compilers;Program processors;Resource management;Runtime;Upper bound},
137. doi={10.1109/12.817393},
138. @ARTICLE{cpu_bypassing_two,
139. volume={57},
140. number={4},
141. pages={433-447},
142. keywords={cache storage;content-addressable storage;access interval predictor;associative caches;bypassing algorithms;counter-based cache replacement;least recently used algorithm;live-time predictor;multilevel caches;theoretical optimal replacement algorithm;Algorithm design and analysis;Counting circuits;Filtering;Pollution;Prediction algorithms;Cache Bypassing;Cache Misses;Cache Replacement;Cache memories;Counter-Based Algorithms},
143. doi={10.1109/TC.2007.70816},
144. ISSN={0018-9340},
145. month={April},}
146. @INPROCEEDINGS{using_cacti_one,
147. author={S. Niar and S. Meftali and J. L. Dekeyser},
148. pages={244-247},
149. keywords={cache storage;electronic engineering computing;embedded systems;integrated circuit design;integrated memory circuits;power consumption;RTL;SystemC description;cache memory design;cache memory module;electronic engineering computing;embedded system simulation;power consumption analytical model;register transfer level;system-on-chip;Cache memory;Design methodology;Electronic packaging thermal management;Embedded system;Energy consumption;Hardware;Libraries;Mobile computing;Power system modeling;Thermal management},
150. doi={10.1109/ICM.2004.1434257},
151. month={Dec},}
152. @misc{nvidia_streams,
153. title = {{GPU Pro Tip: CUDA 7 Streams Simplify Concurrency}},
154. howpublished = "url{https://devblogs.nvidia.com/parallelforall/gpu-pro-tip-cuda-7-streams-simplify-concurrency/}",
155. @misc{amd_ace,
156. howpublished = "url{http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/Asynchronous-Shaders-White-Paper-FINAL.pdf}",
157. @misc{hyperq,
158. title = {{Hyper-Q Example}},
159. howpublished = "url{http://docs.nvidia.com/cuda/samples/6_Advanced/simpleHyperQ/doc/HyperQ.pdf}",
160. @misc{amd_core_next,
161. howpublished = "url{https://www.amd.com/Documents/GCN_Architecture_whitepaper.pdf}",
162. @misc{amd_sdk,
163. author = {AMD},
164. title = {{APP SDK – A Complete Development Platform}},
165. howpublished = "url{http://developer.amd.com/tools-and-sdks/opencl-zone/amd-accelerated-parallel-processing-app-sdk/}",
166. @misc{cacti_tool,
167. author = {HP Labs},
168. title = {{CACTI:An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model}},
169. howpublished = "url{http://www.hpl.hp.com/research/cacti/}",
170. year = {2008},
171. note = "[Online; accessed 20-July-2016]"
172. }
173. @INPROCEEDINGS{data_intensive_app,
174. author={R. Nitu and E. Apostol and V. Cristea},
175. booktitle={Intelligent Computer Communication and Processing (ICCP), 2014 IEEE International Conference on},
176. pages={355-362},
177. keywords={data handling;graphics processing units;GPU MapReduce framework;GPU clusters;GPU programming;MapReduce paradigm;data intensive applications;distributed applications;intensive data processing;large scale computing;Graphics processing units;Kernel;Mars;Memory management;Parallel processing;Process control;Vectors;GPU MapReduce;Hadoop;OpenCL;shared memory},
178. doi={10.1109/ICCP.2014.6937021},
179. month={Sept},}
180. @INPROCEEDINGS{compute_intensive_app,
181. author={G. Teodoro and R. Sachetto and O. Sertel and M. N. Gurcan and W. Meira and U. Catalyurek and R. Ferreira},
182. booktitle={2009 IEEE International Conference on Cluster Computing and Workshops},
183. year={2009},
184. pages={1-10},
185. keywords={coprocessors;digital filters;medical image processing;microcomputers;tumours;Anthill runtime environment;compute intensive applications;distributed execution;dual-core machine;event-driven filters;graphics processing unit;histopathology application;image analysis techniques;multi-core CPUs;neuroblastoma prognosis;octa-core machine;parallel co-processors;standalone execution;Biomedical computing;Cancer;Computer applications;Concurrent computing;Image analysis;Microscopy;Neoplasms;Niobium;Performance analysis;Runtime environment},
186. doi={10.1109/CLUSTR.2009.5289193},
187. ISSN={1552-5244},
188. month={Aug},}