記號連線導向之多階段階層式平面規劃

Interconnection Driven Multistage Hierarchical Floorplanning

10.6358/JCYU.200503.0085

李志宏(Chih-Hung Lee)；傅文佑(Wen-Yu Fu)；張仲喬(Jun-Chiao Chang)；王欽輝(Chin-Huei Wang)；謝財明(Tsai-Ming Hsieh)

叢集 ； 平面規劃 ； 非線性規劃 ； 彈性模組 ； Clustering ； Floorplanning ； Non-linear Programming ； Soft Module

中原學報

33卷1期（2005 / 03 / 01）

85 - 93

繁體中文

在本論文中，我們針對彈性模組藉由整合一個快速且有效的模組置放方法與階層式晶片面積最小化方法而建立出一個新的多階段階層式平面規劃演算法。模組置放方法是由一個以模組間連線關係爲依據的元件填入演算法所構成；當産生模組間的拓樸關係之後，接著應用一個以非線性規劃爲主的階層式晶片面積最小化方法進一步降低晶片面積。此外，在分析連線關係的階段亦能同時考慮關鍵性記號路徑，可藉由賦予較大的權重以解決時脈緊縮(timing closure)問題。實驗結果顯示，我們的演算法可以有效率的使連線總長度最小化並能同時有效降低晶片面積。

In this paper, we present a new multistage hierarchical floorplanning algorithm for soft modules integrated with fast but effective interconnect-driven module placement and hierarchical chip area minimization. The interconnect-driven module placement is achieved by using a fast cell-filling algorithm based on the interconnection relation of nets. When the topology of module locations built by our cell-filling algorithm, a hierarchical chip area minimization algorithm based on non-linear programming is applied to minimize the total chip area. Besides, critical paths or the connective strength of critical nets could be easily enhanced during the step of analyzing interconnection relation for solving timing closure problems. Experimental results show that our multistage hierarchical approach can minimize chip area and total wire length simultaneously in a very efficient way.