對CMOS閘極氧化層線寬為130nm、90nm、65nm時的模擬與分析

The Simulation and Analysis of CMOS Gate Dielectrics for 130nm、90nm、65nm Technology

10.29987/CCUHKJE.200606.0008

陳宜澤(I-Tse Chen)；謝宗原(Zong-Yuan Xie)；馮舉威(Chu-Wei Feng)；邱顯嘉(Xian-Jia Qiu)；胡峻諺(Jim Hu)；譚湘瑜(S.Y. Tan)

二氧化矽SiO2 ； 氮化矽Si3N4 ； 互補金屬氧化物半導體CMOS ； SiO2 ； Si3N4 ； CMOS

華岡工程學報

20期（2006 / 06 / 01）

61 - 68

繁體中文

本專題研究以CMOS氧化層材料（二氧化矽）SiO2、（氮化矽）Si3N4為基材，設計、模擬與分析比較兩者材料在不同線寬狀態與同線寬狀態下，對元件的特性影響。從改變氧化層材料與線寬之方式對元件性能的提升並藉由ISE-TCAD模擬工具來探討。結果顯示，在線寬越做越小的同時，閘極厚度也越做越小，所能承受的電流相對的也跟著減少。當漏電流超過二氧化矽的承受極限時，即會產生穿透現象(Direct Tunneling)，這也就是為什麼90nm製程以下不能使用二氧化矽為材料的原因。

This work is mainly to study two different gate dielectric materials, SiO2 and Si3N4, for advanced CMOS applications. The design, simulation and analysis were based on different gate lengths comparing with these two materials and its device characteristic. As reducing the gate length toward to submicron CMOS device, selecting a gate dielectric material to improve the electric characteristics and been demonstrated by using ISE-TCAD simulation tool. As results, reducing the physical gate size and dielectric thickness, the device can sustain much less electric current. In additional, once leak electric current over the limit of bearing of the silicon, namely is Direct Tunneling. This is the reason that the SiO2 is not a good candidate for sub-90nm CMOS and below.