三維晶片封裝可靠度負載對於奈米元件效能影響之研究

陳建勳

doi:10.6840/cycu201600478

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三维晶片封装可靠度负载对於奈米元件效能影响之研究

Reliability loading impacts of 3D-ICs package on the influence investigation of Nanoscaled device performance.

陈建勳 , 硕士　　导师：李昌骏　　

繁体中文 DOI： 10.6840/cycu201600478

三维晶片封装；矽穿孔；残留应力；应变工程技术；有限元素法； 3D-ICs packaging ； Through Silicon Via (TSV) ； Residual stress ； Strain engineering technology ； Finite element method

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摘要 │ 参考文献 (44) │ 国际计量

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In 1971, Gordon Moore had proposed the Moore's law which predicted the developing of integrated circuit in 44 years. However, the Intel CEO Brian Krzanich has announced that the performance improvements update cycle has extend to two and half years in the near term. It means that the Moore's law for semiconductor industry is not suitable for next generation devices. When the structure geometry of planar type metal oxide semiconductor field transistor (MOSFET) cannot reduce efficiently, one way to increase the transistor density was introduced by three dimensional chips stacking technology. By using the chip stacking technology, transistor density in fixed region can be improved significantly. In three dimensional chips stacking technology, the key point of signal transmission on stacked chips is through silicon via (TSV) structure. 
In this research, the mobility gain of MOSFET which affected by TSV residual tensile stress has been discussed. TSV residual stress appeared during the TSV manufacture process. In the ideal situation, TSV has induced compressive stress which is induced by the coefficient of thermal expansion mismatch between TSV copper and silicon interposer. However in the true situation, TSV structure appeared tensile stress. The TSV residual tensile stress has been considered in this research. Strain engineering technology has been discussed in this research too. In strain engineering technology, germanium or carbon lattice is doped in the source/drain region. By the effect of lattice coefficient mismatch, SiGe or SiC lattice can induce compressive or tensile stress in silicon channel. By using strain engineering technology, MOSFET' carrier mobility has increased and enhance electronic performance. In this research, the influence of temperature loading and the influence of MOSFET position in packaging structure has be considered. Finite element method (FEM) is used to analysis MOSFET channel stress distribution in this research. Furthermore, using piezoresistive coefficient equation, MOSFET mobility gain can be calculate. 
In simulation result, TSV residual tensile stress has increased N-type MOSFET mobility gain. When TSV diameter is 30μm and TSV residual stress has 700MPa tensile stress the N-type MOSFET mobility will increase 5.4%. At the same situation, PMOSFET’s hole carrier mobility has decreased 3%. When the MOSFET position has change in another region, carrier mobility will be change；consider the MOSFET has the same residual stress effect (TSV diameter is 30μm, residual stress is 700MPa ), NMOSFET’s mobility has increased 7% and PMOSFET has decreased 25%. By the simulation result, influences of TSV residual stress and MOSFET position has discussed in this research.

参考文献 ( 44 ) 〈TOP〉

[1]R. A. Robison, “Moore's Law: predictor and driver of the silicon era,” World neurosurgery, vol. 78, no. 5, pp. 399-403, 2012.
连结：
[2]K. Tu, “Reliability challenges in 3D IC packaging technology,” Microelectronics Reliability, vol. 51, no. 3, pp. 517-523, 2011.
连结：
[3]J. U. Knickerbocker, C. S. Patel, P. S. Andry, C. K. Tsang, L. P. Buchwalter, E. J. Sprogis, H. Gan, R. R. Horton, R. J. Polastre, and S. L. Wright, “3-D silicon integration and silicon packaging technology using silicon through-vias,” Solid-State Circuits, IEEE Journal of, vol. 41, no. 8, pp. 1718-1725, 2006.
连结：
[5]S. C. Hong, W. G. Lee, W. J. Kim, J. H. Kim, and J. P. Jung, “Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking,” Microelectronics Reliability, vol. 51, no. 12, pp. 2228-2235, 2011.
连结：
[7]M. Song, L. Chen, and J. A. Szpunar, “Thermomechanical Characteristics of Copper Through-Silicon via Structures,” Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 5, no. 2, pp. 225-231, 2015.
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DOI可强化引用精确性、增强学术圈连结，并给予使用者跨平台的良好使用经验，目前在全世界已有超过五千万个对象申请DOI。如想对DOI的使用与概念有进一步了解，请参考（）。