40奈米LDMOS多路變壓器結合及65奈米CMOS預失真線性器功率放大器之研製

Research of 40nm LDMOS Multi-Way Transformer Combined and 65nm CMOS Pre-Distortion Linearized Power Amplifier

10.6342/NTU201603754

許峰毓

功率放大器 ； 變壓器結合 ； 高電壓操作 ； 線性化功率放大器 ； Power amplifier ； Transformer combining ； High operating voltage ； Pre-distortion power amplifier

臺灣大學電信工程學研究所學位論文

2016年

碩士

黃天偉

英文

隨著無線通訊系統的發展以及半導體製程的演進，以互補式金氧半場效電晶體實現射頻電路以成本優勢逐漸成為市場焦點，其中功率放大器為收發機中最關鍵的電路之一，本論文將著重於互補式金氧半場效電晶體功率放大器之設計與分析。 論文的第二章描述了一個以40奈米橫向雙擴散金氧半場效電晶體製程實現一個1.93-GHz的功率放大器。為了增加功率輸出，採用變壓器電路架構來完成輸出端阻抗匹配，並使用差動電路的架構及中和電容，減少閘級和汲級端的寄生電容，晶片面積為0.620 mm2，此電路達到輸出功率23.1dBm。 論文的第三章描述了以40奈米橫向雙擴散金氧半場效電晶體實現一個5-GHz高輸出功率變壓器結合式放大器，透過電流-電流結合變壓器的技術，將多個變壓器實現在同一區域減少所需要的面積，且有相當好的阻抗平衡，此外還使用放射狀三維架構，減少多路結合需要的面積，進一步將晶片面積縮小。 論文的第四章描述了一個以65奈米互補式金氧半場效電晶體製程實現的29-GHz功率放大器，採用預失真線性化電路並以變壓器電路架構來完成阻抗匹配。此功率放大器使用預失真線性化電路可以改善輸出功率1 dB 壓縮點，進而提升此功率放大器的線性操作範圍。 關鍵字:功率放大器、變壓器結合、高電壓操作、線性化功率放大器

With the development of wireless communication and the evolution of semiconductor process, the radio frequency integrated circuits implemented in CMOS technology become the key point in the industry with low cost advantage. The power amplifier is the most critical component in the transceiver design. Thus the main focus of this thesis is the design and analysis of CMOS power amplifier [31]. The chapter 2 describes a 4G-LTE power amplifier, which is implemented in 40 nm laterally diffused metal oxide semiconductor (LDMOS) CMOS process. To increase the output power, the circuit uses transformer-based matching network for input and output. The proposed PA is designed in a differential common source structure. The neutralization technique is also implemented in this PA design to reduce the intrinsic capacitance from drain to gate. The chip size of the PA is 0.62mm2 and the output saturation power achieves 23.1dBm. The chapter 3 describes a fully-integrated Wi-Fi power amplifier, which is implemented in 40 nm LDMOS process. By current-current combining transformer technique, the multiple transformers can be realized in a compact area with similar port impedance. In addition, the PA uses 3-D radial architecture to reduce the area of multi-way combining. The chapter 4 describes a 29 GHz power amplifier in 65 nm CMOS process. In this work, the PA is designed with pre-distortion linearizer and the circuit uses transformer-based matching networks for input and output network. This power amplifier improves the OP1dB and linearity. Index term-Power amplifier, Transformer combining, High operating voltage, Pre-distortion power amplifier

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