應用於有線及無線系統以數位時間轉換器實現之鎖相迴路及除頻器設計

王敦儒

doi:10.6342/NTU201800326

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应用於有线及无线系统以数位时间转换器实现之锁相回路及除频器设计

Digital-to-Time Converter Based Phase-Locked Loop and Frequency Divider Design for Wireline and Wireless Applications

王敦儒 , 硕士　　导师：林宗贤　　

英文 DOI： 10.6342/NTU201800326

相位选择器；锁相回路；展频；取样锁定；除频器； Phase Selector ； Spread-Spectrum ； Phase-Locked Loop ； Sub-Sampling ； Frequency Divider

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摘要 │ 参考文献 (40) │ 国际计量

摘要〈TOP〉

并列摘要〈TOP〉

Digital-to-Time converters (DTC) have been widely used and it serves as one of the building blocks in many timing applications, such as the fractional-N PLL. The delay is of a DTC is controlled by a digital code, and the amount of delay is usually varied by switching on/off of a set of discrete elements, such as unit delay cells or charging capacitors. This thesis focuses on the applications of DTC.
This thesis includes two works. The first work is “A 1.5-GHz Sub-Sampling Fractional-N PLL for Spread-Spectrum Clock Generator”. This work employs a fractional-N sub-sampling PLL, and supports spread-spectrum clocking. This work aims to reduce the electromagnetic interference (EMI) of a clock generator with its neighboring devices. It is fabricated in TSMC 180-nm CMOS process. Measurement results have shown that the EMI reduction with spread-spectrum clocking enabled is 18.98 dB. Measured RMS jitter of the output signal is 0.88 ps. With a 1.8-V supply voltage, the power consumption is measured to be 11.1 mW.
	The second work is “A 0.635~162.5 MHz Multiple Output Fractional Divider Using Phase Rotating Technique”. This work is realized by phase rotating technique, supporting multiple frequency outputs, with output frequency range of 0.635-162.5 MHz. This work aims to reduce the number of clock generators in a single SoC. It is fabricated in TSMC 90-nm CMOS process. Measurement results show that the proposed fractional divider functions properly under both integer and fractional division. Furthermore, this work supports dual outputs with two different division ratios, realizing a single input, multiple outputs frequency divider.

参考文献 ( 40 ) 〈TOP〉

[1] R. Monteiro, B. Borges and V. Anunciada, “EMI Reduction by Optimizing the Output Voltage Rise Time and Fail Time in High-Frequency Soft-Switching Converters,” in IEEE 35th Annual Power Electronics Specialists Conference, vol.2, pp. 1127-1132, 2004.
连结：
[2] K. Hardin, R. A. Oglesbee and F. Fisher, “Investigation into the Interference Potential of Spread-Spectrum Clock Generation to Broadband Digital Communications,” in IEEE Transactions on Electromagnetic Compatibility, vol. 45, no. 1, pp. 10-21, Feb. 2003.
连结：
[3] H. R. Lee, O. Kim, G. Ahn and D. K. Jeong, “A Low-Jitter 5000ppm Spread Spectrum Clock Generator for Multi-Channel SATA Transceiver in 0.18μm CMOS,” in IEEE International Solid-State Circuits Conference, vol. 1, pp. 162-163, 2005.
连结：
[4] Y. H. Kao and Y. B. Hsieh, “A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial Advanced Technology Attachment Applications Using Two-Point Modulation,” in IEEE Transactions on Electromagnetic Compatibility, vol. 51, no. 2, pp. 245-254, May 2009.
连结：
[5] S. Jang, S. Kim, S. H. Chu, G. S. Jeong, Y. Kim and D. K. Jeong, “An All-Digital Bang-Bang PLL Using Two-Point Modulation and Background Gain Calibration for Spread Spectrum Clock Generation,” in Symposium on VLSI Circuits, pp. C136-C137, 2015.
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使用DOI作为永久连结

引用含有DOI的文献

DOI可强化引用精确性、增强学术圈连结，并给予使用者跨平台的良好使用经验，目前在全世界已有超过五千万个对象申请DOI。 如想对DOI的使用与概念有进一步了解，请参考 （ ） 。

DOI可强化引用精确性、增强学术圈连结，并给予使用者跨平台的良好使用经验，目前在全世界已有超过五千万个对象申请DOI。如想对DOI的使用与概念有进一步了解，请参考（）。